Luciano M. Almeida

The Dependence of Retention Time on Gate Length in UTBOX FBRAM With Different Source/Drain Junction Engineering

The floating-body-RAM sense margin and retention-time dependence on the gate length is investigated in UTBOX devices using BJT programming combined with a positive back bias (so-called V th feedback). It is shown that the sense margin and the retention time can be kept constant versus the gate length by using a positive back bias. Nevertheless, below a critical L, there is no room for optimization, and the memory performances suddenly drop. The mechanism behind this degradation is attributed to GIDL current amplification by the lateral bipolar transistor with a narrow base. The gate length can be further scaled using underlap junctions.

Junction Field Effect on the Retention Time for One-Transistor Floating-Body RAM

One-transistor floating-body random access memory retention time distribution is investigated on silicon-on-insulator UTBOX devices. It is shown that the average retention time can be improved by two to three orders of magnitude by reducing the body-junction electric field. However, the retention time distribution, which is mainly caused by the generation-recombination center density variation, remains similar.

Dependence of Generation–Recombination Noise With Gate Voltage in FD SOI MOSFETs

A model for computing the generation-recombination noise due to traps within the semiconductor film of fully depleted silicon-on-insulator MOSFET transistors is presented. Dependence of the corner frequency of the Lorentzian spectra on the gate voltage is addressed in this paper, which is different to the constant behavior expected for bulk transistors. The shift in the corner frequency makes the characterization process easier. It helps to identify the energy position, capture cross sections, and densities of the traps. This characterization task is carried out considering noise measurements of two different candidate structures for single-transistor dynamic random access memory devices.

The impact of gate length scaling on UTBOX FDSOI devices: The digital/analog performance of extension-less structures

In this paper we explore, from DC measurements, the impact of gate length scaling on the main digital/analog parameters of Ultra-Thin Buried Oxide (UTBOX) Fully Depleted Silicon-on-Insulator (FDSOI) devices at different temperatures. Standard junction reference devices are compared with the extension-less ones where the latter present superior characteristics for smaller device lengths such as improved DIBL, SS and IGIDL apart from the higher Ion/Ioff ratio, VEA and AV. The temperature tends to degrade all the device parameters although the extension-less structures show to be less susceptible to its influence.

Temperature influence on UTBOX 1T-DRAM using GIDL for writing operation

This paper investigates the temperature influence on Ultra Thin Buried Oxide (UTBOX) FDSOI devices used as a 1T-DRAM (single transistor dynamic random access memory cell) using GIDL (Gate Induced Drain Leakage) for writing operation through numerical simulations. At higher temperatures, it is observed that the memory window varies and the retention time is degraded, when using a standard read. To solve this issue, we suggest the ZTC read, which fixes the state-0 current independently of the temperature. Moreover, considering I0 current as a reference current for the memory cell operation results in improved retention time.

Comparison between low and high read bias in FB-RAM on UTBOX FDSOI devices

This paper investigates the drain read bias impact on the FB-BRAM performance of Ultra Thin Buried Oxide (UTBOX) Fully Depleted Silicon On Insulator (FDSOI) devices. Both simulations and experimental results are used. Two read regimes are clearly observed. In the read regime at higher drain voltage, impact ionization is occurring and this result in a higher sense margin and a lower retention time compared to the low drain voltage read regime.

Resultados clínicos iniciais do primeiro stent de cromo-cobalto concebido no Brasil

Initial Clinical Results of the First Cobalt-Chromium Stent Designed in Brazil Background: Thin-strut cobalt-chromium stents have greater flexibility and probably have less neointimal proliferation than stainless steel stents. Methods: The Cronus (Scitech Produtos Medicos, Goiânia, Brazil) registry is an international, non-randomized, prospective study designed to evaluate the efficacy and safety of a novel thin-strut cobalt-chromium stent in patients with coronary artery disease. A total of 69 lesions were treated in 53 patients included in this analysis. Results: The device success was 98.5%. Mean late luminal loss was 0.7 ± 0.5 mm, binary restenosis occurred in 15% and target vessel revascularization in 11.3% of the cases. The incidence of major adverse cardiac events (death, myocardial infarction or target vessel revascularization) was 24.4% after 317 ± 80 days of follow-up. Conclusion: Our initial results demonstrate that the novel Cronus stent proved to be safe and effective, with clinical results similar to other available thin-strut stents. DESCRIPTORS: Stents. Angioplasty, transluminal, percutaneous coronary. Prostheses and implants.

Zero-Temperature-Coefficient of planar and MuGFET SOI devices

The Zero Temperature Coefficient (ZTC) is investigated experimentally in planar and standard/biaxially strained triple-gate nFinFETs fabricated on SOI wafers. In this work a simple model to analyze the behavior of the gate-source voltage at the Zero Temperature Coefficient point (VZTC) is proposed in the linear and saturation operation regions. The analysis takes into account the temperature variations of the threshold voltage and the transconductance degradation factor. Although simple, the model predictions are in good agreement with the experimental results.

Back gate bias influence on SOI Ω-gate nanowire down to 10 nm width

We investigate for the first time the influence of the back gate bias (VB) in the main digital and analog parameters on Silicon-On-Insulator (SOI) omega-gate nanowire devices down to 10 nm width (W). For wider channel, it was observed that for high negative VB the subthreshold swing (SS) and DIBL are decreased due to the better channel confinement while the intrinsic voltage gain is almost insensitive in all studied devices. For omega-gate nanowire of 10 nm width, no relevant influence was observed in both digital and analog parameters, once that for 11 nm height and rounded structure it is working effectively like a gate all around structure.

Zero Temperature Coefficient behavior for advanced MOSFETs

In this work the Zero Temperature Coefficient (ZTC) is investigated experimentally using state-of-the-art industrial technologies like Ultra-Thin Body and Buried Oxide (UTBB) and triple-gate FinFETs (irradiated and/or strained devices), both fabricated on Silicon On Insulator (SOI) wafers. A simple analytical model to analyze the behavior of the gate-source voltage at the Zero Temperature Coefficient point (VZTC) is validated for these advanced devices. Although simple, the model predictions have shown good agreement with the experimental results and can be useful for low-power low-voltage analog circuit designers, where biasing at/near the ZTC point should result in low thermal drift of the circuit operation.