Kayvan Sadra

Variations in timing and leakage power of 45nm library cells due to lithography and stress effects

We have conducted a study of context-dependent variability for cells in a 45nm library, including both lithography and stress effects, using the Cadence Litho Electrical Analyzer (LEA) software. Here, we present sample data and address a number of questions that arise in such simulations. These questions include identification of stress effects causing context dependence, impact of the number of contexts on the results, and combining lithography-induced variations due to overlay error with context-dependent variations. Results of such simulations can be used to drive a number of corrective and adaptive actions, among them layout modification, cell placement restrictions, or optimal design margin determination.

Variable-threshold optical proximity correction (OPC) models for high-performance 0.18-μm process

The recent development of lithographic resolution enhancement techniques of optical proximity correction (OPC) and phase shift masks (PSM) enable sprinting critical dimension (CD) features that are significantly smaller than the exposure wavelength. In this paper, we present a variable threshold OPC model that describes how a pattern configuration transfers to the wafer after resist and etch processes. This 0.18 micrometers CMOS technology utilizes isolation with pitches of active device regions below 0.5 micrometers . The effective gate length on silicon is in the range of 0.11 to 0.18 micrometers . The OPC model begins with a Hopkins formula for aerial image calculation and is tuned to fit the measured CD data, using a commercially available software. The OPC models are anchored at a set of selected CD dat including linearity, line-end pullback, and linewidth as a function of pitch. It is found that the threshold values inferred from measured CD dat vary approximately linearly with the slope of aerial image. The accuracy of the model is illustrated by comparing the simulated contour using the OPC model and measured SEM image. The implementation of OPC models at both active and gate is achieved using two approaches: (1) to optimize the mask bias and sizes of hammerhead and serifs via a rule based approach; and (2) to correct the SRAM cell layouts by OPC model. The OPC models developed have been successfully applied to 0.18 micrometers technology in a prototyping environment.