Brian Hornung

Modeling the effect of source/drain sidewall spacer process on boron ultra shallow junctions

A novel model is developed to explain the effect of the source/drain sidewall spacer process on boron drain extension formation. A diffusion model for hydrogen in the source/drain sidewall spacer is developed and combined with a model for boron diffusion in oxides. The model is first calibrated to hydrogen out-diffusion data from Nuclear Reaction Analysis (NRA) and then to boron diffusion data from Secondary Ion Mass Spectroscopy (SIMS). Seemingly anomalous changes in boron junction depths with variation in sidewall spacer deposition conditions are explained by this model. The model is applied to TCAD process/device simulations to understand the effect of sidewall spacer on CMOS device performance.

Variations in timing and leakage power of 45nm library cells due to lithography and stress effects

We have conducted a study of context-dependent variability for cells in a 45nm library, including both lithography and stress effects, using the Cadence Litho Electrical Analyzer (LEA) software. Here, we present sample data and address a number of questions that arise in such simulations. These questions include identification of stress effects causing context dependence, impact of the number of contexts on the results, and combining lithography-induced variations due to overlay error with context-dependent variations. Results of such simulations can be used to drive a number of corrective and adaptive actions, among them layout modification, cell placement restrictions, or optimal design margin determination.

Continuum Modeling of Indium to Predict SSR Profiles

Indium (In) diffusion and dose-loss in silicon is modeled in a continuum simulator. The model includes the large segregation of In to End of Range (EOR) defects, and the dissolution of these defects resulting in dose-loss of In at the surface. The models developed are successfully applied to predict state of the art (90 nm) transistor performance.