Kazuhiko Shimakawa
Panasonic
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Publication
Featured researches published by Kazuhiko Shimakawa.
international electron devices meeting | 2008
Zhiqiang Wei; Yoshihiko Kanzawa; K. Arita; Yoshikazu Katoh; Ken Kawai; Shunsaku Muraoka; S. Mitani; Satoru Fujii; Koji Katayama; M. Iijima; Takumi Mikawa; Takeki Ninomiya; R. Miyanaga; Y. Kawashima; K. Tsuji; Atsushi Himeno; T. Okada; Ryotaro Azuma; Kazuhiko Shimakawa; H. Sugaya; Takeshi Takagi; R. Yasuhara; K. Horiba; H. Kumigashira; Masaharu Oshima
Highly reliable TaOx ReRAM has been successfully demonstrated. The memory cell shows stable pulse switching with endurance over 109 cycles, sufficient retention exceeding 10 years at 85degC. TaOx exhibits stable high and low resistance states based on the redox reaction mechanism, confirmed by HX-PES directly for the first time. An 8 kbit 1T1R memory array with a good operating window has been fabricated using the standard 0.18 mum CMOS process.
international solid-state circuits conference | 2012
Akifumi Kawahara; Ryotaro Azuma; Yuuichirou Ikeda; Ken Kawai; Yoshikazu Katoh; Kouhei Tanabe; Toshihiro Nakamura; Yoshihiko Sumimoto; Naoki Yamada; Nobuyuki Nakai; Shoji Sakamoto; Yukio Hayakawa; Kiyotaka Tsuji; Shinichi Yoneda; Atsushi Himeno; Kenichi Origasa; Kazuhiko Shimakawa; Takeshi Takagi; Takumi Mikawa; Kunitoshi Aono
Nonvolatile memories with fast write operation at low voltage are required as storage devices to exceed flash memory performance. We develop an 8Mb multi-layered cross-point ReRAM macro with 443MB/S write throughput (64b parallel write per 17.2ns cycle), which is almost twice as fast as existing methods, using the fast-switching performance of TaOχ ReRAM and the following three techniques to reduce the sneak current in bipolar type cross-point cell array structure in an 0.18μm process. First, memory cell and array technologies reduce the sneak current with a newly developed bidirectional diode as a memory cell select element for the first time. Second, we use a hierarchical bitline (BL) structure for multi-layered cross-point memory with fast and stable current control. Third, we implement a multi-bit write architecture that realizes fast write operation and suppresses sneak current. This work is applicable to both high-density stand-alone and embedded memory with more stacked memory arrays and/or scaling memory cells.
international electron devices meeting | 2011
Z. Wei; Takeshi Takagi; Yoshihiko Kanzawa; Yoshikazu Katoh; Takeki Ninomiya; Ken Kawai; Shunsaku Muraoka; Satoru Mitani; Koji Katayama; Satoru Fujii; Ryoko Miyanaga; Yoshio Kawashima; Takumi Mikawa; Kazuhiko Shimakawa; Kunitoshi Aono
A new oxygen diffusion reliability model for a high-density bipolar ReRAM is developed based on hopping conduction in filaments, which allows statistical predication of activation energy. The filament in the active cells is confirmed by EBAC and TEM directly for the first time. With optimized filament size, a 256-kbit ReRAM with long-term retention exceeding 10 years at 85°C is successfully demonstrated.
international electron devices meeting | 2007
Shunsaku Muraoka; K. Osano; Yoshihiko Kanzawa; Satoru Mitani; Satoru Fujii; Koji Katayama; Yoshikazu Katoh; Z. Wei; Takumi Mikawa; K. Arita; Yoshio Kawashima; Ryotaro Azuma; Ken Kawai; Kazuhiko Shimakawa; A. Odagawa; Takeshi Takagi
A novel iron oxide (Fe-O) ReRAM is proposed and its high-speed resistance-switching of 10 ns is demonstrated. The switching mechanism is confirmed as a redox reaction between Fe<sub>3</sub>O<sub>4</sub> and y-Fe<sub>2</sub>O<sub>3</sub>. Based on this model, we have achieved long-retention characteristics by introducing Zn atoms to suppress the reduction process.
symposium on vlsi technology | 2012
Takeki Ninomiya; Takeshi Takagi; Z. Wei; Shunsaku Muraoka; Ryutaro Yasuhara; Koji Katayama; Yuuichirou Ikeda; Ken Kawai; Y. Kato; Yoshio Kawashima; S. Ito; Takumi Mikawa; Kazuhiko Shimakawa; Kunitoshi Aono
We demonstrate for the first time that the density of oxygen vacancy in a conductive filament plays a key role in ensuring data retention. We achieve very good retention results up to 100 hours at 150°C even under the low current operation due to the scaling of conductive filament size while retaining sufficiently high density of oxygen vacancy.
international solid-state circuits conference | 2013
Akifumi Kawahara; Ken Kawai; Yuuichirou Ikeda; Yoshikazu Katoh; Ryotaro Azuma; Yuhei Yoshimoto; Kouhei Tanabe; Zhiqiang Wei; Takeki Ninomiya; Koji Katayama; Ryutaro Yasuhara; Shunsaku Muraoka; Atsushi Himeno; Naoki Yoshikawa; Hideaki Murase; Kazuhiko Shimakawa; Takeshi Takagi; Takumi Mikawa; Kunitoshi Aono
Resistive RAM (ReRAM) has been recently developed for applications that require higher speed and lower voltage than Flash memory is able to provide. One of the applications is micro-controller units (MCUs) or SoCs with several megabits of embedded ReRAM. Another is solid-state drives (SSDs) where a combination of higher-density ReRAM and NAND flash memory would achieve high-performance and high-reliability storage [1], suitable for server applications for future cloud computing. ReRAM is attractive for several reasons. First, it operates at high speed and low voltage. Second, it enables high density due to the simple structure of the resistive element (RE) [2]. Third, it is immune to external environment such as magnetic fields or radiation, since the resistive switching is based on the redox reaction [3].
international memory workshop | 2012
Z. Wei; Takeshi Takagi; Yoshihiko Kanzawa; Yoshikazu Katoh; Takeki Ninomiya; Ken Kawai; Shunsaku Muraoka; Satoru Mitani; Koji Katayama; Satoru Fujii; Ryoko Miyanaga; Yoshio Kawashima; Takumi Mikawa; Kazuhiko Shimakawa; Kunitoshi Aono
A retention model for both the high resistance state and low resistance state of the bipolar ReRAM is developed. Degradation of resistance is caused by the oxygen vacancy profile in filament changing due to oxygen diffusion.
international solid-state circuits conference | 2005
Masahisa Iida; Naoki Kuroda; Hidefumi Otsuka; Masanobu Hirose; Yuji Yamasaki; Kiyoto Ohta; Kazuhiko Shimakawa; Takashi Nakabayashi; Hiroyuki Yamauchi; Tomohiko Sano; Takayuki Gyohten; Masanao Maruta; Akira Yamazaki; Fukashi Morishita; Katsumi Dosaka; Masahiko Takeuchi; Kazutami Arimoto
A 16 Mb embedded DRAM macro in a fully CMOS logic compatible 90 nm process with a low noise core architecture and a high-accuracy post-fabrication tuning scheme has been developed. Based on the proposed techniques, 61% improvement of the sensing accuracy is realized. Even with the smallest 5 fF/cell capacitance, a 322 MHz random-cycle access while 32 ms data retention time which contributes to save the data retention power down to 60 /spl mu/W are achieved.
international electron devices meeting | 2015
Zhiqiang Wei; Koji Eriguchi; Shunsaku Muraoka; Koji Katayama; Ryutaro Yasuhara; Ken Kawai; Yuuichirou Ikeda; M. Yoshimura; Yukio Hayakawa; Kazuhiko Shimakawa; Takumi Mikawa; Shinichi Yoneda
A physical analytic formula based on Stochastic Differential Equation was successfully developed to describe intrinsic ReRAM variation. The formula was proved useful for projecting scaled ReRAM memory window and resistance distribution after long-term retention, verified by testing 40 nm 2-Mbit ReRAM. The formula also centered on practical and quantitative filament characterization.
international conference on ic design and technology | 2014
Ken Kawai; Akifumi Kawahara; Ryutaro Yasuhara; Shunsaku Muraoka; Zhiqiang Wei; Ryotaro Azuma; Kouhei Tanabe; Kazuhiko Shimakawa
ReRAM is increasingly being developed for applications that require higher speeds and lower voltages than flash memory. We have found TaOx to have high performance and high reliability. However one of the phenomena observed in ReRAM is that each resistance after Set and Reset varies during every cycle. To stabilize resistive switching, the key is to limit these variations in resistance. In ReRAM, a conductive filament (CF) is created by the forming pulse. Resistive switching in the CF is based on reduction and oxidization using this voltage pulse. This paper reviews a hopping percolation model which we have proposed for the switching process, and this paper proposes an automatic forming circuit using our newly-developed externally-scalable forming pulse (ESF) scheme. In this CF model, conductive paths show different conductivities caused by the formation of different percolation networks that link hopping sites. Larger CFs show greater variation in resistance due to the many possible combinations of percolation networks. This makes it important to develop a forming technique that limits CFs to their optimal size. Forming is based on dielectric breakdown, so the pulse width ranges over approximately three orders. The automatic forming circuit detects, bit by bit, whether forming is over, and stops the forming pulse after a specified period. A forming pulse is then generated, using an external clock, to cover the range of pulse widths. This allows the filament size to be controlled to ensure it is uniform for all of the bits in the circuit, at the cost of only a small area overhead.