Kazuhito Higuchi

Low-Stress Interconnection for Flip Chip BGA Employing Lead-Free Solder Bump

Flip chip bonding technology has been widely used for interconnection in high-end logic LSI employing lead-rich solder bumps. Recently, from an environmental issue, it is desired that the lead-rich solder should be replaced by lead-free solder. However, the stress at the interconnection after flip chip bonding reflow cannot be relaxed with lead-free solder bumps because of their poor creep properties. Since the stress causes delamination of the low-k layer under bumps and electrical open errors, the improvement of the solder bump material and the flip chip bonding process have been necessary for stress relaxation. In this study, we investigated the creep properties of Sn-0.7Cu and Sn-3.5Ag bumps by the indentation method. As a result, it was found that the creep properties of Sn-0.7Cu bumps was more suitable for stress relaxation than those of Sn-3.5Ag. Moreover, we confirmed that a low-stress interconnection had been achieved by employing Sn-0.7Cu bumps. The stress at the interconnection was less than the delaminating stress of the low-k layer. In addition, when the flip chip bonding was carried out by the reflow with the post-annealing, in which the temperature was held for a period of time at 200degC during reflow cooling part, the maximum stress in the low-k layer has been reduced by more than 36% in comparison with the low-k delaminating stress. Furthermore, it was found that the stresses at the flip chip joints were relaxed because of the increase of the creep rate which was caused by the reflow with the post-annealing.

MCM-D/L using copper/photosensitive-BCB multilayer for upper microwave band systems

This paper describes an MCM-D/L technology for upper microwave band systems. The substrate of this MCM is constructed of copper/photosensitive-benzocyclobutene (P-BCB) multilayer formatted onto a print wiring board (PWB). Features of the developed MCM are (1) a novel microstrip structure for improvement of high-frequency characteristics and (2) a low-cost simple copper/P-BCB process using polishing technology. As BCB has good thermal and electric characteristics compared with polyimide or epoxy, BCB is expected to be applied to high frequency systems. We have developed a low-cost copper/P-BCB multilayer process with a new microstrip structure, and measured the high-frequency characteristics (10 GHz/spl sim/40 GHz). In the process technology, we took note of the adhesion of the metal film/BCB interface. As a result of a study of the adhesive metal and chemical/thermal treatment before and after fabrication of the film, we found that the necessary adhesion force was obtained by N/sub 2/ plasma treatment of the BCB surface before metal evaporation and annealing (250/spl deg/C:BCB cure temperature) after evaporation. Also, Cr was found to be the best material for adhesion. The high-frequency characteristics (10 GHz/spl sim/40 GHz) were estimated by a ring resonator and microstrip transmission line of copper/P-BCB multilayer fabricated on a PWB. Also, the S-parameters showed good characteristics. The developed MCM-D/L substrate has been proved to be suitable for high-frequency systems.

A fully integrated novel Wafer-Level LED package (WL2P) technology for extremely low-cost solid state lighting devices

Reduction of cost has become the most important challenge for solid state lighting. We proposed a novel Wafer-Level LED Packaging (WL2P) technology, which enables both extremely low cost and small size for future solid state lighting. Where a conventional package needs individual assembly steps, resulting in high fabrication cost, we carried out from growth of the GaN layer, over formation of Inter Layer Dielectric (ILD), wiring for solder pad to printing the phosphor layer on a whole wafer in our WL2P. Thus, for the first time a fully integrated wafer-level process was successfully applied to light emitting diode (LED) devices. It was clearly demonstrated that our WL2P has an excellent thermal resistance as low as 24.2K/W in the 0.6×0.3mm size prototype structure because of the direct connection of Cu wiring to the light emitting layer and a maximum injection power density was as high as 1157W/cm2 in a difference of 50°C between junction temperature and ambient temperature on the aluminum based printed wiring board (PCB)

Dilute Cu Alloying for Sn-Cu Bumping by Annealing Electroplated Cu/Sn Stacks on Ti/Ni/Pd UBM

Sn-Cu bumping has been demonstrated to employ sequential electroplating of Cu and Sn, followed by alloying the Cu/Sn stacks during reflow. Alloying behavior of the Cu/Sn stacks has been investigated with varying the underlying Cu thickness. The Cu6Sn5 based compounds were observed at the interface between a sputter deposited Ti/Ni/Pd under bump metallization and the Cu/Sn plated stack The underlying Cu was consumed by forming the intermetallic compounds as well as alloying with Sn, limiting the alloying Cu content in the Sn-Cu bump. With elevating reflow temperature, the alloying Cu content in the bump was slightly decreased. The result cannot be predicted by the solubility limit of Cu into Sn at a given reflow temperature based on the equilibrium phase diagram. The basic process design for the Cu/Sn stack has been provided. The intermetallic phase has been confirmed to work as a good diffusion barrier to Sn, leading to integrity of the Ni after solid state aging. The Cu/Sn stack plating process allows us to realize dilute Cu alloying with Sn for the eutectic composition and less Cu contents in the Sn-Cu bumps. In the bumping process, the thickness ratio of the Cu/Sn stack as plated does not need to be strictly controlled and a thick electrodeposited Ni layer is not necessary as the under bump metallization. This study confirms that electroplating provides a robust and cost-effective process for mass production of lead free bumping

Novel wafer-level CSP for stacked MEMS / IC dies with hermetic sealing

Novel wafer-level chip scale package (WL-CSP) applicable to configurations involving stacking of multiple dies has been developed. Since stacked die makes high topography and it is difficult to apply conventional WL-CSP process, gold bonding wires were used for not only connecting stacked dies with one another but also for connecting from each die to CSP terminals. The WL-CSP is also applicable to microelecrromechanical system (MEMS) that requires hermetic sealing. Thin-film encapsulation for MEMS was formed by conventional back end of line (BEOL) process. Followed by die stacking and gold wire forming, chemical vapor deposition (CVD) was applied to make hermetic sealing. The WL-CSP does not require photolithography process on topography wafer. It promises a cost-effective solution for MEMS/IC dies coupled device.

Optical characteristics and reliability evaluation of wafer level white LED package

In this paper, we describe optical characteristics and reliability of a novel wafer level white LED (light-emitting diode) package. In this package, re-distribution wiring layer and phosphor layer could be formed in a lump by wafer level process. As a result, ultrasmall size package that is almost same size as the chip could be attained. This approach results in drastic reduction in material and process cost. We determined the package structure from the results of the numerical analysis on the thermal cycle resistance of the package after reflow soldering. The sapphire substrate is removed by laser process and the GaN layer exists between phosphor layer and encapsulation resin. Applicative light extraction was achieved by control of GaN surface roughness. In addition, it was confirmed that the package had sufficient reliability in the thermal cycle test (TCT). Consequently, this low cost package could be applicable to LED components and also the cost of them is considered to drastically decrease.

A novel wafer dicing method using metal-assisted chemical etching

A novel wafer dicing method that can singulate silicon wafers into individual dies at once has been developed. Since this method relies on chemical reactions, we call it Chemical Dicing. Chemical Dicing has the advantages of high throughput, narrow dicing line width, and high chip strength compared to conventional blade dicing methods. Chemical Dicing is based on the catalytic wet etching technique called metal-assisted chemical etching (MacEtch). However, the appropriate conditions required to form deep vertical trenches for Chemical Dicing with MacEtch remain controversial. In this paper, the MacEtch mechanisms and appropriate conditions for Chemical Dicing have been verified. The results show that the shape of the trenches can be controlled by a catalyst and a etchant composition, and Chemical Dicing can create vertical trenches with a depth greater than 150 μm and width less than 8 μm. The results are expected to contribute to the development of future dicing techniques.

Ag plating and its impact on void-free Ag/Sn bumping

We have already developed the eutectic Sn-Ag solder bumping process by alloying Ag/Sn electroplated metal stacks to overcome some problems concerning Sn-Ag alloy plating. As the dimensions of solder bumps shrink, the effect of voids in the solder bumps on electromigration resistance must be discussed. For the Sn-Ag alloy plated bumps, voids in the solder bumps as reflow processed are difficult to be avoided. The large amount of degassed species from the alloy-plated bumps due to strong chemical agents trapped in the plated films has a close relation to generation of voids in the bumps. In contrast, though the stack plating process shows less degassing, micro-voids would be left at the interface of the plated stack as embryos of residual voids in the solder bumps. In this study, surface roughness of the underlying Ag films and degassing behavior of the Ag/Sn stack-plated bumps has been investigated using different types of Ag plating solutions. Gas analyses and X-ray imaging inspections were performed for the Ag/Sn plated stacks. Surface roughness of the underlying Ag layer was also characterized by a laser scanning and scanning electron microscopy. From the experimental results, it has been confirmed that less degassing is the most important issue for the Ag/Sn plated stacks. In addition, improvement of surface roughness of the underlying Ag plated films must not be neglected.