Kan Takeuchi

Measurement of neutron-induced single event transient pulse width narrower than 100ps

A novel SET pulse measurement circuit is proposed which can detect pulses narrower than 100ps. Alternation of SET pulses during the propagation through the chain of target cells is minimized, which is attributed to small chain length (typically 20). This circuit configuration contributes to obtaining pulse distribution similar to that observed in actual circuit in use. Distribution of SET pulse width measured by our circuit through the white neutron beam testing agrees well with that estimated by computer simulation.

Probabilistic crosstalk delay estimation for ASICs

The crosstalk delay caused by capacitive coupling between wires on a chip is investigated by using a statistical approach and circuit simulations. Two metrics are introduced in order to evaluate an impact of the crosstalk delay on timing design in advance. The first is probabilistic coupling rate (CPR), which can be obtained by the short segment model of the aggressors. Then, the CPR roughly obeys normal distribution and its standard deviation is determined by the slew time of the victim along with the number of aggressor segments. The second is crosstalk delay normalized by the original delay without crosstalk, /spl Delta/t/sub pd//t/sub pd/. The /spl Delta/t/sub pd//t/sub pd/ is equal to 2*CPR at the maximum, and CPR on average, regardless of victim length. The two metrics in conjunction with empirical slew distribution allows us to set the appropriate crosstalk delay budget, at the prelayout stage, for reducing the possibility of the crosstalk violation found in the postlayout verification process.

Scaling effect and circuit type dependence of neutron induced single event transient

Neutron induced single event transient (SET) has been measured on NAND and inverter (INV) chain with changing fan-out, drive strength, size of drain diffusion area, temperature and VDD on 40nm and 90nm bulk CMOS technology. As the pulse width distribution varies with the length of SET target chain as well, it is important to use the chain length similar with the actual logic circuits. Using tens of stages of target chain, pulses wider than 150ps have been rarely observed. The results of the measurement show that the SER of SET changes depending on the cell type and fan-out. SER of SET in combinational logic circuits decreases by half from 90nm to 40nm for the same gate count and the same clock frequency.

Study on Influence of Device Structure Dimensions and Profiles on Charge Collection Current Causing SET Pulse Leading to Soft Errors in Logic Circuits

Current responses due to the strike of ionized particle onto nMOS transistor of 90nm and 55nm generation have been analyzed through 3D device simulations. From the current response, duration of charge collection (tcc) is determined, which correlated strongly with the width of erroneous pulse (SET pulse). Causes of the difference between tcc values of 90nm and 55nm generation MOSFETs have been investigated and it is found that the difference in STI depth and width of p-well contact line between these two generations influences tcc mainly. This is because that the resistance below the p-well contact affects the ability to pull out the excess holes remaining in the channel region. It is also shown that there is room for reducing tcc and hence SET pulse width by well profile engineering. I. INTRODUCTION Neutron-induced soft error phenomena have received much attention since they are considered as one of the major ob- stacles to realize highly reliable LSIs. Although Single-Event- Upset observed in memory circuits such as SRAMs and flip- flops is still major concern, soft error phenomena occurring in combinational-logic circuits can be more serious in future technology node (1). In the logic circuits, propagation of erroneous signal, called Single-Event-Transient (SET), occurs and the erroneous signal might be finally stored, for instance, in a flip-flop as illustrated in Fig. 1. The wider the SET pulse is, the more probably the erroneous signal is stored. Such a SET pulse is initially caused by collection of generated charge due to the impact of the ionized particle. In this paper, duration of charge collection is evaluated which is related to SET pulse width strongly, and its dependence on device structure dimensions and profiles is investigated.

An on-die digital aging monitor against HCI and xBTI in 16 nm Fin-FET bulk CMOS technology

We propose an on-die aging monitor based on ring-oscillator (RO) which measures bias-temperature-instabilities (BTI) and AC hot-carrier-infection (HCI). The monitor consists of a symmetric RO (SRO) and an asymmetric RO (ASRO). The effect of NBTI and PBTI can be separated by focusing on the difference in sensitivity observed in SRO and ASRO under DC stress condition. In addition, the speed degradation caused by AC-HCI is monitored because unbalanced delay with long/short transition in ASRO has high sensitivity against AC-HCI under AC stress. A test chip including both SRO and ASRO using 2NAND standard cells is implemented in a 16 nm Fin-FET bulk CMOS technology. We observe that Vth shift due to PBTI measured from frequency degradation is 2 mV, which is still 1/10 of NBTI in Fin-FET technology. The measured AC-HCI shows almost half percentage of all aging factors. The aging monitor optimizes the design guard band (GB) in design phase and enables dependable system in high performance application LSIs.

Clock-Skew Test Module for Exploring Reliable Clock-Distribution Under Process and Global Voltage-Temperature Variations

This paper presents a clock-skew test module for exploring reliable clock distribution under process, voltage, and temperature (PVT) variations. The proposed test module enables direct evaluation of the following two important issues: 1) the clock-skew process variations and 2) the robustness against race problems under environmental variations such as voltages and temperatures. The test module was fabricated by using a 90-nm low-power process for system-on-chip (SoC). It contains eight blocks including H-tree blocks and clock tree synthesis (CTS)-tree blocks (i.e., blocks formed by clock-tree synthesis), each of which has 1024 flip-flop (FF) pairs with small hold-time margins. A statistical method has been developed for analyzing the measured hold-time margins of the 1024 FF pairs for 80 chips. The example of the analysis for the measured results is presented, confirming the effectiveness of the proposed test module and analysis method toward reliable design of clock distribution.

Observations of Supply-Voltage-Noise Dispersion in Sub-nsec

This paper describes observations of supply-voltage-noise dispersion by using a test structure fabricated with a 65-nm low-power process. The test structure can capture the phenomenon in two domains: One is a space domain. The 1 kbit probes distributed uniformly over the entire test-module region detect the spread of the noise, which is induced in the center of the module. The noise is generated by simultaneous activation of 8 kbit flip-flops (FF), which are placed in a dense area. Each delay probe consists of a short buffer-chain between a pair of FFs to detect the delay shift caused by voltage drop in the area. The other is a time domain. The probes being different in the length of the buffer-chains can capture the time dependency. The measurement results have revealed how the supply-voltage-noise spreads over the entire test-module region in a very short time (sub-nsec).

A voltage drop aware crosstalk measurement with multi-aggressors in 65nm process

An efficient crosstalk delay degradation measurement method with a 65 nm process is proposed. The voltage drop impact on the crosstalk delay is measured. The test module incorporates filters which omit glitches high speed complicated circuits unintentionally create. The module consists of standard cells only, that makes designing very easy. An intensive comparison of measured results with simulations for 64 times 216 patterns of six aggressor activations (timing and combinations) shows precise matching with less than 10% errors.

Wear-out stress monitor utilising temperature and voltage sensitive ring oscillators

The authors propose an on-chip wear-out monitoring technique, which is based on monitoring the environmental conditions experienced by a digital circuit. The frequency of the T-sensitive ring oscillator (RO) emulates the wear-out stress strength caused by the temperature conditions based on the model of exponential dependence of the stress on the inverse of temperatures. The frequency of the VT-sensitive RO emulates the stress due to time-dependent dielectric breakdown, which is stressed by voltages as well as temperatures. Thus, the accumulated counts driven by the ROs directly indicate the total wear-out stress that the product has experienced so far. The measured results of a test chip fabricated by 28 nm High-k Metal Gate process confirm the expected dependence of T-/VT-sensitive RO frequencies on temperatures and voltages, enabling the emulation of wear-out. The methodology is presented to estimate the stress amount of various wear-out factors having different thermal activation energies. The proposed wear-out stress monitor would make automotive microcontrollers more reliable when they operate at boosted voltages and elevated temperatures to meet performance requirements of cutting-edge applications such as advanced driver assistance systems.

FEOL/BEOL wear-out estimator using stress-to-frequency conversion of voltage/temperature-sensitive ring oscillators for 28nm automotive MCUs

We propose wear-out estimator of remaining lifetime, which consists of two types of custom ring oscillators (ROs) and cumulative stress counters only. This on-chip estimator operates independently without disruption of MCU main operations and is aimed for advanced automotive MCUs, which demand sufficient reliability and real-time response along with high performance in cutting-edge applications such as ADAS. One of the custom ROs is temperature sensitive RO, which achieves the count-up speed proportional to exp(-Ea/kT), thus enabling estimation of the accumulated electro-migration (EM) stress that the die has experienced thus far. The other RO is voltage and temperature sensitive RO, which achieves the count-up speed proportional to Vn*exp(-Ea/kT) for use in TDDB stress estimation. The test chip of the custom ROs was fabricated by using 28nm HKMG process. The measured result successfully emulates more than one order of magnitude difference between 125C and 85C EM stress and 10× combinational accentuation of TDDB stress under simultaneous high voltage and temperature.