Kazunori Ohuchi

A 4 Mb NAND EEPROM with tight programmed V/sub t/ distribution

Described is a 5-V-only 4-Mb (512K*8 b) NAND EEPROM (electrically erasable programmable ROM) with tight programmed threshold voltage (V/sub t/) distribution, controlled by a novel program-verify technique. A tight programmed V/sub t/ distribution width of 0.8 V for the 4 Mb cell array is achieved. By introducing a compact row-decoder circuit, a die size of 7.28 mm*15.31 mm is achieved using 1.0 mu m design rules. A unique twin p-well structure has made it possible to realize low-power 5 V-only erase/program operation easily and to achieve 100 K-cycle endurance. >

An experimental 16-Mbit CMOS DRAM chip with a 100-MHz serial read/write mode

A 5-V 4M-word*4-b dynamic RAM (random-access memory) with a 100-MHz serial read/write mode using 0.7- mu m triple-tub CMOS technology is discussed. The RAM utilizes a recently developed STT (stacked trench capacitor) cell which achieved 37 fF in a small cell size of 1.7*3.6 mu m/sup 2/. The STD (sidewall transistor with double-doped drain) structure is used for PMOS-FETs to realize high-speed operation. To ensure MOSFET reliability, the 5-V external supply voltage is converted to a 4-V internal supply voltage by an on-chip voltage converter circuit. An on-chip interleaved circuit and double-input-buffer scheme is used to realize high-speed serial read/write operation. Using an external 5-V power supply, the RAM achieved a 100-MHz serial access cycle, and RAS access time is 70 ns. The typical active current is 120 mA at a 190-ns cycle time. >

Open/folded bit-line arrangement for ultra-high-density DRAM's

An open/folded bit-line (BL) arrangement for scaled DRAMs is proposed. This BL arrangement offers small die size and good array noise immunity. In this arrangement, one BL of an open BL pair is placed in between a folded BL pair, and the sense amplifiers (SAs) for open BLs and those for folded BLs are placed alternately between the memory arrays. This arrangement features a small 6F/sup 2/ memory cell, where F is the device feature size, and a relaxed SA pitch of 6F. The die size of a 64-Mb DRAM can be reduced to 81.6% compared with the one using the conventional folded BL arrangement. The BL-BL coupling noise is reduced to one-half of that of the conventional folded BL arrangement, thanks to the shield effect. Two new circuit techniques, 1) a multiplexer for connecting BLs to SAs, and 2) a binary-to-ternary code converter for the multiplexer have been developed to realize the new BL arrangement. >

New nibbled-page architecture for high-density DRAMs

A nibbled-page architecture which can be used to access all column addresses on the selected row address randomly in units of 8 bits at the 100 Mbit/s data rate is discussed. To realize such high-speed architecture, three key circuit techniques have been developed. An on-chip interleaved circuit has been used for the high-speed serial READ and WRITE operations. Column address prefetch and WE signal prefetch techniques have been introduced to eliminate idle time between 8 bit units. The nibbled-page architecture has been successfully implemented in an experimental 16 Mb DRAM, and 100 Mb/s operation has been achieved. The DRAM with nibbled-page mode is very effective in simplifying the design of high-speed data transfer systems. >

A new static memory cell based on reverse base current (RBC) effect of bipolar transistor

A novel SRAM (static random access memory) cell, which consists of a bipolar transistor and an MOS transistor, is proposed. The device, which is based on the reverse base current (RBC) effect, has been fabricated by conventional BiCMOS technology, using double poly-Si. A cell size of 8.58 mu m/sup 2/ has been realized in a 1.0- mu m ground rule. The results indicate that the RBC cell can be applied to very-high-density SRAMs, as large as 16 Mb or beyond.<<ETX>>

A high-density NAND EEPROM with block-page programming for microcomputer applications

A high-density, 5-V-only, 4-Mb CMOS EEPROM with a NAND-structured cell using Fowler-Nordheim tunneling for programming is discussed. The block-page mode is utilized for high-speed programming and easy microprocessor interface. On-chip test circuits for shortening test time and for evaluating cell characteristics yield highly reliable EEPROMs. The NAND EEPROM has many applications for microcomputer systems that require small size and large nonvolatile storage systems with low power consumption. >

An experimental 4Mb CMOS DRAM

technology developments were performed, in addition to the use of previously-established technologies, some of which have been demonstrated for 1 M CMOS DRAMs”~. The RAM was fabricated in a twintub CMOS process with 1 . 0 ~ design rules, which are affordable minimum limits for VLSIs obtained by present aligners. The array consists of trenched, N-channel, depletion-type capacitor cells in a P-well, which helps to reduce soft error rate314. Figure 1 shows a cross-sectional SEM microphotograph of the cell. Cell storage capacitance is 40fF with a 31-1 deep trench. Even though they are not necessari1y needed for Vcc/2 for precharged bitlines, dummy cells having a full memory cell capacitance and Vcc /2 level are adopted making the sense amplifiers less susceptible to bitline precharge level variations. Memory cell, dummy cell, and sense amplifier circuitry are shown in Figure 2. Considering a transition from llrl to 4M, many problems become more serious. One of these problems is operating current. The RAM is divided into eight 512K blocks. Together with Vcc/2 bitline precharge, one fourth of the blocks is activated during each RAS operating cycle to reduce power dissipation due to bitline discharge. However, the active current and especially the peak current are still not small enough to neglect since these are causes of V c c and VSS noise. Thus, an exclusive power supply wiring technique for sense amplifiers is applied to avoid the effect of bitline discharge and reduce current noise in peripheral circuit operation. Since memory test time markedly increases with memory size, the RAM has an 8b parallel test mode operation which suppresses the RAM test time. This mode is available for both x1 and x4 packaged device testing as well as for die sort testing. The test mode is activated by applying a high voltage to an extra TEN (test enable) pad. To obtain a high quality 4M DRAM, several new circuit and process

Standby/active mode logic for sub-1-V operating ULSI memory

New gate logics, standby/active mode logic I and II, for future 1 Gb/4 Gb DRAMs and battery operated memories are proposed. The circuits realize sub-l-V supply voltage operation with a small 1-/spl mu/A standby subthreshold leakage current, by allowing 1 mA leakage in the active cycle. Logic I is composed of logic gates using dual threshold voltage (Vt) transistors, and it can achieve low standby leakage by adopting high Vt transistors only to transistors which cause a standby leakage current. Logic II uses dual supply voltage lines, and reduces the standby leakage by controlling the supply voltage of transistors dissipating a standby leakage current. The gate delay of logic I is reduced by 30-37% at the supply voltage of 1.5-1.0 V, and the gate delay of logic II is reduced by 40-85% at the supply voltage of 1.5-0.8 V, as compared to that of the conventional CMOS logic. >

A 33-ns 64-Mb DRAM

A 64-Mb CMOS dynamic RAM (DRAM) measuring 176.4 mm/sup 2/ has been fabricated using a 0.4- mu m N-substrate triple-well CMOS, double-poly, double-polycide, double-metal process technology. The asymmetrical stacked-trench capacitor (AST) cells, 0.9 mu m*1.7 mu m each, are laid out in a PMOS centered interdigitated twisted bit-line (PCITBL) scheme that achieves both low noise and high packing density. Three circuit techniques were developed to meet high-speed requirements. Using the preboosted word-line drive-line technique, a bypassed sense-amplifier drive-line scheme, and a quasi-static data transfer technique, a typical RAS access time of 33 ns and a typical column address access time of 15 ns have been achieved. >

A sub-10-ns 16/spl times/16 multiplier using 0.6-/spl mu/m CMOS technology

A 16/spl times/16-b parallel multiplier fabricated in a 0.6-/spl mu/m CMOS technology is described. The chip uses a modified array scheme incorporated with a Booths algorithm to reduce the number of adding stages of partial products. The combination of scaled 0.6-/spl mu/m CMOS technology and advanced arithmetic architecture achieves a multiplication time of 7.4 ns while dissipating only 400 mW. This multiplication time is shorter than other MOS high-speed multipliers previously reported and is comparable to those for advanced bipolar and GaAs multipliers.