Masaki Momodomi

New ultra high density EPROM and flash EEPROM with NAND structure cell

In order to realize ultra high density EPROM and Flash EEPROM, a NAND structure cell is proposed. This new structure is able to shrink cell size without scaling of device dimensions. The NAND structure cell realizes a cell as small as 6.43 µm2using 1.0 µm design rule. As a result, cell area per bit can be reduced by 30% compared with that of a 4M bit EPROM using the conventional structure and the same design rule. It is confirmed that each bit in a NAND cell is able to be programmed selectively. This high performance NAND structure cell is applicable to high density nonvolatile memories as large as 8M bit EPROM and Flash-EEPROM or beyond.

A 4 Mb NAND EEPROM with tight programmed V/sub t/ distribution

Described is a 5-V-only 4-Mb (512K*8 b) NAND EEPROM (electrically erasable programmable ROM) with tight programmed threshold voltage (V/sub t/) distribution, controlled by a novel program-verify technique. A tight programmed V/sub t/ distribution width of 0.8 V for the 4 Mb cell array is achieved. By introducing a compact row-decoder circuit, a die size of 7.28 mm*15.31 mm is achieved using 1.0 mu m design rules. A unique twin p-well structure has made it possible to realize low-power 5 V-only erase/program operation easily and to achieve 100 K-cycle endurance. >

An accurate model of subbreakdown due to band-to-band tunneling and some applications

The authors describe a novel accurate model and numerical analysis of subbreakdown phenomena due to band-to-band tunneling in a thin-gate-oxide n-MOSFET. Subbreakdown I-V characteristics are calculated for various oxide thicknesses. The results agree with experimental results over a wide range of subbreakdown current from 10/sup -12/ A to 10/sup -6/ A. The numerical analysis based on this model has been utilized to suppress the subbreakdown current. It is concluded that the model can be utilized for the design of thin-gate-oxide devices. >

A high-density NAND EEPROM with block-page programming for microcomputer applications

A high-density, 5-V-only, 4-Mb CMOS EEPROM with a NAND-structured cell using Fowler-Nordheim tunneling for programming is discussed. The block-page mode is utilized for high-speed programming and easy microprocessor interface. On-chip test circuits for shortening test time and for evaluating cell characteristics yield highly reliable EEPROMs. The NAND EEPROM has many applications for microcomputer systems that require small size and large nonvolatile storage systems with low power consumption. >

A 35 ns cycle time 3.3 V only 32 Mb NAND flash EEPROM

A 32 Mb NAND type flash EEPROM in 0.425 /spl mu/m CMOS achieves 35 ns cycle time for data read-out and programming data load by adopting a pipeline scheme. Metal-strapped select gates and boosted word line reduce read-out access time. Tight-programmed cell Vth distribution can be realized by program verify, using a simplified data register circuit. Multiple blocks can be erased at the same time by adopting erase block registers for each block. Simultaneous-erase verify for one block reduces total erase time. All funtions require only 3.3 V power supply.

A 2.3 mu m/sup 2/ memory cell structure for 16 Mb NAND EEPROMs

A NAND structure memory cell with 2.2*1.05 mu m/sup 2/ size per bit, based on a 0.6 mu m design rule, has been developed for 16 Mb flash EEPROMs. The cell size is about 64% of the smallest 16 Mb EPROM cell so far reported. An extremely small cell can be realized by the following technologies: (1) newly developed 0.3 mu m space self-aligned stacked gate patterning, (2) a NAND structured cell array which contains 16 memory transistors in series, and (3) high-voltage field isolation technology used to isolate neighboring bits. The first and second technologies reduce the length of the cell by 67.6% compared with the conventional NAND structured cell using the same design rule, while the third technology reduces the width by 84.6%.<<ETX>>

Analysis of LDD transistor asymmetry susceptibility in VLSI circuits

This paper describes problems due to asymmetry of source and drain impurity profile caused by the shadowing of ion beams by gate electrodes. This asymmetry degrades the sensitivity of sense amplifiers especially when Lightly-Doped-Drain/Source (LDD) transistors are adopted. This effect is a serious obstacle to realize ultra high density DRAMs. In order to reduce this effect, a sensing circuit suppressing the asymmetry effect is proposed and its sensitivity improvement is evaluated.

An Advanced NAND-Structure Cell Technology for Reliable 3.3 V 64 Mb Electrically Erasable and Programmable Read Only Memories (EEPROMs)

An extremely small NAND-structure cell of 1.13 µm2 per bit, 80% of the smallest Flash memory cell reported so far [H. Kume et al.: IEEE Tech. Dig. IEDM (1992) p. 991], has been developed in 0.4 µm technology. The chip size of a 64 Mb NAND electrically erasable and programmable read only memory (EEPROM) using this cell is estimated to be 120 mm2, which is 60% that of a 64 Mb DRAM. In order to realize the small cell size, a 0.8 µm field isolation is used. A negative bias of -0.5 V to the P-well of the memory cell is applied during writing. In addition, a bit-by-bit intelligent writing technology allows a 3.3 V data sensing scheme which can suppress read disturb to 1/1000 in comparison with the conventional 5 V scheme. As a result, it is expected that with this technology, 106 write and erase cycles can be achieved and that the tunnel oxide can be scaled down from 10 nm to 8 nm.

A high density NAND EEPROM with block-page programming for microcomputer applications

A 5 V-only 4 Mb NAND EEPROM (electrically erasable programmable read-only memory) has been successfully developed. The EEPROM has on-chip high-voltage generators, so the system needs only a 5 V power supply. The block-page erase/program mode realizes high-speed programming. On-chip test circuits provide high reliability. The NAND EEPROM has many applications for compact microcomputer systems, which need large storage systems with low power consumption

New device technologies for 5 V-only 4 Mb EEPROM with NAND structure cell

Novel device technologies for a 5-V-only EEPROM (electrically erasable programmable read-only memory) with a NAND structure cell are described. By applying half of the programming voltage to unselected bit lines and a successive programming sequence, the NAND structure cell keeps a wide threshold margin. A high-voltage CMOS process realizes reliable programming characteristics. The reliability of the cell has been confirmed experimentally. Using 1.0- mu m design rules, the unit cell area per bit is 12.9- mu m/sup 2/, which is small enough to realize a 4-Mb EEPROM.<<ETX>>