Yoshihisa Iwata

Bit Cost Scalable Technology with Punch and Plug Process for Ultra High Density Flash Memory

We propose Bit-Cost Scalable (BiCS) technology which realizes a multi-stacked memory array with a few constant critical lithography steps regardless of number of stacked layer to keep a continuous reduction of bit cost. In this technology, whole stack of electrode plate is punched through and plugged by another electrode material. SONOS type flash technology is successfully applied to achieve BiCS flash memory. Its cell array concept, fabrication process and characteristics of key features are presented.

Memory design using one-transistor gain cell on SOI

A 512 kb DRAM has a 7F/sup 2/ one-transistor gain cell (F=0.18 /spl mu/m) on SOI. The array driving method makes selective write possible. Basic operation is verified by device simulation and hardware measurement. Simulations show 40 ns access time. Non-destructive readout and Cb/Cs-free signal development improve cell efficiency.

New ultra high density EPROM and flash EEPROM with NAND structure cell

In order to realize ultra high density EPROM and Flash EEPROM, a NAND structure cell is proposed. This new structure is able to shrink cell size without scaling of device dimensions. The NAND structure cell realizes a cell as small as 6.43 µm2using 1.0 µm design rule. As a result, cell area per bit can be reduced by 30% compared with that of a 4M bit EPROM using the conventional structure and the same design rule. It is confirmed that each bit in a NAND cell is able to be programmed selectively. This high performance NAND structure cell is applicable to high density nonvolatile memories as large as 8M bit EPROM and Flash-EEPROM or beyond.

Optimal device structure for Pipe-shaped BiCS Flash memory for ultra high density storage device with excellent performance and reliability

An asymmetric source/drain profile for select gate and metal salicided control gate are successfully realized on Pipe-shaped Bit Cost Scalable (P-BiCS) Flash memory to achieve data storage device with excellent performance and reliability.

A 4 Mb NAND EEPROM with tight programmed V/sub t/ distribution

Described is a 5-V-only 4-Mb (512K*8 b) NAND EEPROM (electrically erasable programmable ROM) with tight programmed threshold voltage (V/sub t/) distribution, controlled by a novel program-verify technique. A tight programmed V/sub t/ distribution width of 0.8 V for the 4 Mb cell array is achieved. By introducing a compact row-decoder circuit, a die size of 7.28 mm*15.31 mm is achieved using 1.0 mu m design rules. A unique twin p-well structure has made it possible to realize low-power 5 V-only erase/program operation easily and to achieve 100 K-cycle endurance. >

A novel sense amplifier for flexible voltage operation NAND flash memories

This paper proposes a new bit-by-bit verify circuit for application in NAND flash memories. The Sense Amplifier (S/A) employed confers two benefits: flexible power supply voltage (ex. 3 V or 5 V) operation with a high noise immunity and an intelligent page copy function. The benefits are very useful to the flash memory card or system and accelerate the replacement of magnetic memories by flash memories. The S/A has been successfully implemented in the commercial version of the 32 Mbit NAND-EEPROM, in which the S/A is newly introduced in comparison with the prototype version.

A high-density NAND EEPROM with block-page programming for microcomputer applications

A high-density, 5-V-only, 4-Mb CMOS EEPROM with a NAND-structured cell using Fowler-Nordheim tunneling for programming is discussed. The block-page mode is utilized for high-speed programming and easy microprocessor interface. On-chip test circuits for shortening test time and for evaluating cell characteristics yield highly reliable EEPROMs. The NAND EEPROM has many applications for microcomputer systems that require small size and large nonvolatile storage systems with low power consumption. >

A 35 ns cycle time 3.3 V only 32 Mb NAND flash EEPROM

A 32 Mb NAND type flash EEPROM in 0.425 /spl mu/m CMOS achieves 35 ns cycle time for data read-out and programming data load by adopting a pipeline scheme. Metal-strapped select gates and boosted word line reduce read-out access time. Tight-programmed cell Vth distribution can be realized by program verify, using a simplified data register circuit. Multiple blocks can be erased at the same time by adopting erase block registers for each block. Simultaneous-erase verify for one block reduces total erase time. All funtions require only 3.3 V power supply.

A 4-Mbit NAND-EEPROM with tight programmed V t distribution

The authors describe a 4-Mb NAND-EEPROM with tight Vt (threshold voltage) distribution which is controlled by a novel program verify technique. A tight Vt distribution width of 0.6 V for the entire 4-Mb cell array is achieved, and read margin is improved. A unique twin p-well structure has made it possible to realize low-power 5-V-only erase/program operation easily compared with the previous design

Design and process integration for high-density, high-speed, and low-power 6F/sup 2/ cross point MRAM cell

A cross point (CP) cell with hierarchical bit line architecture was proposed for magnetoresistive random access memory (MRAM) based in Y. Shimizu et al. (2004). The new CP cell has a potential high density of 6F/sup 2/ and a faster access time than the conventional CP cell. A cell layout design to realize 6F is proposed and associated issues are resolved. Further, a 1Mb MRAM chip based on this structure has been fabricated utilizing 0.13 /spl mu/m CMOS technology and 0.24/spl times/0.48 /spl mu/m/sup 2/ magnetic tunnel junction (MTJ) sandwiched with the most efficient yoke wires ever reported. The access time of 250 ns and 1.5 V operations are successfully demonstrated with the integrated 1Mb chip.