Yukihito Oowaki

A novel circuit technology with surrounding gate transistors (SGT's) for ultra high density DRAM's

This paper describes a novel circuit technology with Surrounding Gate Transistors (SGTs) For ultra high density DRAMs. In order to reduce the chip size drastically, an SGT is employed to all the transistors within a chip. SGTs connected in series and a common source SGT have been newly developed for the core circuit, such as a sense amplifier designed by a tight design rule. Furthermore, to reduce the inherent cell array noise caused by a relaxed open bit line (BL) architecture, a noise killer circuit placed in the word line (WL) shunt region and a twisted BL architecture within the sense amplifier region combined with a novel separation sensing scheme have been newly introduced. Using the novel circuit technology, a 32.9% smaller chip size can be successfully achieved for a 64-Mb DRAM and 34.4% for a 1-Gb DRAM compared with a DRAM composed of the planar transistor without sacrificing the access time, power dissipation, and V/sub cc/ margin. Furthermore,the effectiveness of this technology is verified by using the circuit simulation of the internal main nodes such as WL and BL. >

A 0.5 V 200 MHz 1-stage 32 b ALU using a body bias controlled SOI pass-gate logic

SOI CMOS with gate-body connection (DTMOS) and body bias controlled SOI pass-gate logic (BCSOI pass-gate) take advantage of individually isolated SOI device active area and reduce threshold voltage by controlling each device body bias. Hence, they enjoy higher speed than circuits based on fixed low threshold voltage. The direct body bias control used in previous work suffers from leakage current at supply voltage higher than 0.8V due to drain-body junction leakage. A practical circuit technology that offers the highest speed, lowest operation voltage and stable operation under wide supply voltage demonstrates performance with an ALU macro using this technology.

Conditional Data Mapping Flip-Flops for Low-Power and High-Performance Systems

This paper introduces a new family of low-power and high-performance flip-flops, namely conditional data mapping flip-flops (CDMFFs), which reduce their dynamic power by mapping their inputs to a configuration that eliminates redundant internal transitions. We present two CDMFFs, having differential and single-ended structures, respectively, and compare them to the state-of-the-art flip-flops. The results indicate that both CDMFFs have the best power-delay product in their groups, respectively. In the aspect of power dissipation, the single-ended and differential CDMFFs consume the least power at data activity less than 50%, and are 31% and 26% less power than the conditional capture flip-flops at 25% data activity, respectively. In the aspect of performance, CDMFFs achieve small data-to-output delays, comparable to those of the transmission-gate pulsed latch and the modified-sense-amplifier flip-flop. In the aspect of timing reliability, CDMFFs have the best internal race immunity among pulse-triggered flip-flops. A post-layout case study is demonstrated with comparison to a transmission-gate flip-flop. The results indicate the single-ended CDMFF has 34% less in data-to-output delay and 28% less in power at 25% data activity, in spite of the 34% increase in size

An experimental 16-Mbit CMOS DRAM chip with a 100-MHz serial read/write mode

A 5-V 4M-word*4-b dynamic RAM (random-access memory) with a 100-MHz serial read/write mode using 0.7- mu m triple-tub CMOS technology is discussed. The RAM utilizes a recently developed STT (stacked trench capacitor) cell which achieved 37 fF in a small cell size of 1.7*3.6 mu m/sup 2/. The STD (sidewall transistor with double-doped drain) structure is used for PMOS-FETs to realize high-speed operation. To ensure MOSFET reliability, the 5-V external supply voltage is converted to a 4-V internal supply voltage by an on-chip voltage converter circuit. An on-chip interleaved circuit and double-input-buffer scheme is used to realize high-speed serial read/write operation. Using an external 5-V power supply, the RAM achieved a 100-MHz serial access cycle, and RAS access time is 70 ns. The typical active current is 120 mA at a 190-ns cycle time. >

A 63-mW H.264/MPEG-4 audio/visual codec LSI with module-wise dynamic Voltage/frequency scaling

A single-chip H.264 and MPEG-4 audio-visual LSI for mobile applications including terrestrial digital broadcasting system (ISDB-T / DVB-H) with a module-wise, dynamic voltage/frequency scaling architecture is presented for the first time. This LSI can keep operating even during the voltage/frequency transition, so there is no performance overhead. It is realized through a dynamic deskewing system and an on-chip voltage regulator with slew rate control. By the combination with traditional low power techniques such as embedded DRAM and clock gating, it consumes only 63 mW in decoding QVGA H.264 video at 15 frames/sec and MPEG-4 AAC LC audio simultaneously.

Open/folded bit-line arrangement for ultra-high-density DRAM's

An open/folded bit-line (BL) arrangement for scaled DRAMs is proposed. This BL arrangement offers small die size and good array noise immunity. In this arrangement, one BL of an open BL pair is placed in between a folded BL pair, and the sense amplifiers (SAs) for open BLs and those for folded BLs are placed alternately between the memory arrays. This arrangement features a small 6F/sup 2/ memory cell, where F is the device feature size, and a relaxed SA pitch of 6F. The die size of a 64-Mb DRAM can be reduced to 81.6% compared with the one using the conventional folded BL arrangement. The BL-BL coupling noise is reduced to one-half of that of the conventional folded BL arrangement, thanks to the shield effect. Two new circuit techniques, 1) a multiplexer for connecting BLs to SAs, and 2) a binary-to-ternary code converter for the multiplexer have been developed to realize the new BL arrangement. >

0.5 V SOI CMOS pass-gate logic

Demand for low-power ULSIs for mobile electronic equipment is increasing rapidly. To reduce power consumption, lower operating voltage and minimized device size (or count) is essential. To lower the actual threshold voltage and lower the operation voltage, SOI MOSFET with gate-body connection is proposed. However, the circuit architecture that affords the maximum advantage of the body controlled SOI MOSFET has not yet been reported. The SOI CMOS pass-gate logic described here offers the lowest operation voltage and reduced transistor dimensions. In this logic the body of the SOI pass-gate is connected to the input signal given to the gate. Low threshold voltage for the onstate pass-gate and high threshold voltage for the off-state passgate is realized, and the increase in the threshold voltage due to the body-effect is suppressed. Two types of buffer suitable for SOI pass-gate logic are examined.

New nibbled-page architecture for high-density DRAMs

A nibbled-page architecture which can be used to access all column addresses on the selected row address randomly in units of 8 bits at the 100 Mbit/s data rate is discussed. To realize such high-speed architecture, three key circuit techniques have been developed. An on-chip interleaved circuit has been used for the high-speed serial READ and WRITE operations. Column address prefetch and WE signal prefetch techniques have been introduced to eliminate idle time between 8 bit units. The nibbled-page architecture has been successfully implemented in an experimental 16 Mb DRAM, and 100 Mb/s operation has been achieved. The DRAM with nibbled-page mode is very effective in simplifying the design of high-speed data transfer systems. >

Standby/active mode logic for sub-1-V operating ULSI memory

New gate logics, standby/active mode logic I and II, for future 1 Gb/4 Gb DRAMs and battery operated memories are proposed. The circuits realize sub-l-V supply voltage operation with a small 1-/spl mu/A standby subthreshold leakage current, by allowing 1 mA leakage in the active cycle. Logic I is composed of logic gates using dual threshold voltage (Vt) transistors, and it can achieve low standby leakage by adopting high Vt transistors only to transistors which cause a standby leakage current. Logic II uses dual supply voltage lines, and reduces the standby leakage by controlling the supply voltage of transistors dissipating a standby leakage current. The gate delay of logic I is reduced by 30-37% at the supply voltage of 1.5-1.0 V, and the gate delay of logic II is reduced by 40-85% at the supply voltage of 1.5-0.8 V, as compared to that of the conventional CMOS logic. >

An experimental DRAM with a NAND-structured cell

An experimental 256-Mb dynamic random access memory using a NAND-structured cell (NAND DRAM) has been fabricated. The NAND-structured cell has four memory cells connected in series, which reduces the area of isolation between the adjacent cells and also reduces the bit-line contact area. The cell area per bit measures 0.962 mu m/sup 2/, using 0.4- mu m CMOS technology, which is 63% in comparison with the conventional cell. In order to reduce the die size, time division multiplex sense-amplifier (TMS) architecture, in which a sense amplifier is shared by four bit lines, has been newly introduced. The chip area is 464 mm/sup 2/, which is 68% compared with the DRAM using the current cell structure. The data can be accessed by a fast-block-access mode up to 512 bytes as well as a random access mode. Typical 112-ns access time of the first data in a block and 30-ns serial cycle time are achieved. >