Kazuo Nojiri

Predicting synergy in atomic layer etching

Atomic layer etching (ALE) is a multistep process used today in manufacturing for removing ultrathin layers of material. In this article, the authors report on ALE of Si, Ge, C, W, GaN, and SiO2 using a directional (anisotropic) plasma-enhanced approach. The authors analyze these systems by defining an “ALE synergy” parameter which quantifies the degree to which a process approaches the ideal ALE regime. This parameter is inspired by the ion-neutral synergy concept introduced in the 1979 paper by Coburn and Winters [J. Appl. Phys. 50, 5 (1979)]. ALE synergy is related to the energetics of underlying surface interactions and is understood in terms of energy criteria for the energy barriers involved in the reactions. Synergistic behavior is observed for all of the systems studied, with each exhibiting behavior unique to the reactant–material combination. By systematically studying atomic layer etching of a group of materials, the authors show that ALE synergy scales with the surface binding energy of the bu...

Atomic layer etching of GaN and AlGaN using directional plasma-enhanced approach

The directional atomic layer etching (ALE) of GaN and AlGaN has been developed. The GaN ALE process consists of cyclic Cl2 plasma chemisorption and Ar ion removal. The etch per cycle (EPC) was 0.4 nm within the self-limiting regime, which is 50 to 100 V. The root-mean-square surface roughness R RMS was 0.6 nm, which was improved from an initial roughness of 0.8 nm. For AlGaN ALE, BCl3 was added to the chlorine step to obtain a smooth surface with R RMS of 0.3 nm and stoichiometry similar to the initial sample. The ultra smooth surface obtained by etching is promising for use in next-generation power devices.

Mechanism of Dry Etching

A guiding principle for designing a dry etching process has yet to be established. However, guidelines for designing a process may be obtained by examining the reaction processes. For that, one must first understand the mechanism of dry etching. This chapter starts with the basics of plasma and goes on to describe the dry etching reaction processes and the mechanism of anisotropic etching without relying on mathematical equations or difficult theories, in a way that is completely accessible to readers who have no background in dry etching.

Latest Dry Etching Technologies

This chapter reviews the latest etching technologies, including Cu damascene etching, low-κ etching, metal gate/high-κ etching, and FinFET etching. There are also discussions on the various methods of Cu damascene etching as well as the methods of preventing damage to low-κ films, which become a serious issue at the 32-nm node and beyond. Furthermore, the discussion includes a review of the double-patterning technology, which is the hot topic of the moment, and three-dimensional integrated circuit (3D IC) etching for the 16-nm node and beyond.

Dry Etching of Various Materials

This chapter reviews the etching of materials actually used in the semiconductor manufacturing process. Etching used in the semiconductor process may be categorized into (1) etching of Si, (2) etching of insulators, and (3) etching of metal line materials. In this chapter, the key technologies in each category—which are gate etching, SiO2 etching for holes, spacer etching, and etching of Al alloy stacked metal layer structures—are described in detail. The discussions delve beyond simple descriptions and include the information that will help the reader understand the key parameters for the etching process and how to control them. The chapter has been designed so that once the reader understands these etching processes, the knowledge may be applied to the etching of other materials. For example, a section on gate etching reviews the etching of the poly–Si gate, WSi2/poly–Si gate, and W/WN/poly–Si gate. Once the reader understands these completely, then a similar approach may be followed for designing an etching process for shallow trench isolation (STI) and W metal lines. Also, with gate etching, there is a strong need not only to control the etch profile, but also to minimize the pattern size nonuniformity across the wafer. A discussion on this issue includes which parameters dominate the pattern size uniformity across the wafer and how to control them.

Dry Etching Equipment

This chapter first reviews the history of dry etching equipment. Then it provides detailed discussions of the basic mechanisms of plasma generation, plasma density, operating pressure conditions, and key characteristics of dry etching equipment used in LSI manufacturing today, including the barrel-type plasma etcher, capacitively coupled plasma (CCP) etcher, magnetron reactive-ion etching (RIE), electron-cyclotron resonance (ECR) plasma etcher, and inductively coupled plasma (ICP) etcher. Finally, the electrostatic chuck, which plays an important role in dry etching equipment, is discussed.

Future Challenges and Outlook for Dry Etching Technology

The author joined the semiconductor industry in 1975. Combined with his 3 earlier years spent on semiconductor research in college and in graduate school, the author’s total involvement with semiconductors has spanned approximately 40 years. During that time, semiconductor technology has made incredible advances in terms of device scaling, density increases, and larger wafer diameters. As mentioned in Chap. 1, the device minimum feature size has been shrunk by approximately 30 % every 3 years, and the LSI device density has been increasing pretty much according to Moore’s law. In 1975, when the author first started in the semiconductor industry, a large number of discrete bipolar transistors were still in manufacturing, and 16K DRAM, based on the 5-μm process, was just about to begin. As of 2011, logic devices and memory products, with minimum feature sizes of 32–28 nm, had gone into volume production. This means that minimum feature sizes were scaled to 1/200 in 36 years. At the same time, the number of transistors on each microprocessor chip grew by approximately 100,000-fold. Furthermore, the Si wafer diameter, which used to be 75 mm in 1975, had grown to 300 mm. It is a different world today.

Dry Etching Damage

Dry etching has been a key technology in the LSI manufacturing process, and the high integration of LSI would not have been realized without progress in this technology. However, because the process uses plasma, the devices are susceptible to various types of damages caused by high-energy and charged particles. A large amount of damage sometimes lowers the LSI yields and reliability.

The Contribution of Dry Etching Technology to Progress in Semiconductor Integrated Circuits

Advances in the computer industry in recent years, as seen in the rapid commercialization of advanced information systems such as multimedia devices, is underpinned by various large-scale integration (LSI) devices such as microprocessors and memory. The LSI technology is advancing very rapidly, as shown in Fig. 1.1, with the device density doubling approximately every 2 years [1]. The transistor count in Fig. 1.1 refers to the number of transistors on each microprocessor chip, and this trend toward higher device density follows Moore’s law. Minimum feature sizes are shrunk approximately 30 % every 3 years, and logic devices and flash memory products, with 32-nm-level minimum feature sizes, were in volume production as of 2011. Some 28-nm production devices are also available as of this writing.