Kazushi Miki

Self-assembled nanowires on semiconductor surfaces

A number of different families of nanowires which self-assemble on semiconductor surfaces have been identified in recent years. They are particularly interesting from the standpoint of nanoelectronics, which seeks non-lithographic ways of creating interconnects at the nm scale (though possibly for carrying signal rather than current), as well as from the standpoint of traditional materials science and surface science. We survey these families and consider their physical and electronic structure, as well as their formation and reactivity. Particular attention is paid to rare earth nanowires and the Bi nanoline, both of which self-assemble on Si(001).

Observation of Si(001) Vicinal Surfaces on RHEED

We have used reflection high‐energy electron diffraction to characterize the surface step structure of Si(001) vicinal surfaces tilted from 0.5° to 4° toward the [110] azimuth. The surface of small misorientation (0.5°, 1°) after a high‐temperature anneal was double‐domain with monolayer steps, while that of a large misorientation (4°) was single‐domain with bilayer steps. The single‐domain structure appeared for all samples during homoepitaxial growth. For surfaces tilted by 0.5° or 1°, the selective growth of the first half of a monolayer was observed which changed the surface from double‐domain with monolayer steps to single‐domain with bilayer steps.

Interaction between electronic structure and strain in Bi nanolines on Si(001)

Heteroepitaxial strain can be a controlling factor in the lateral dimensions of 1-D nanostructures. Bi nanolines on Si(001) have an atomic structure which involves a large sub-surface reconstruction, resulting in a strong elastic coupling to the surrounding silicon. We present variable-bias STM and first principles electronic structure calculations of the Bi nanolines, which investigates this interaction. We show that the strain associated with the nanolines affects the atomic and electronic structure of at least two neighbouring Si dimers, and identify the mechanism behind this. We also present partial charge densities (projected by energy) for the nanoline with clean and hydrogenated surroundings and contrast it to the clean Si(001) surface.

An experimental-theoretical study of the behaviour of hydrogen on the Si(001) surface

An understanding of the dynamics of hydrogen on Si(001) is crucial to understanding gas-source growth, as the presence of hydrogen on the surface during gas-source growth of silicon and germanium dramatically changes the kinetics of growth and the morphology of the growth surface. We have used a combination of hot scanning tunnelling microscopy experiments and computational modelling, with the two techniques inter-relating, to investigate this system. By comparison with experimental and ab initio results, we have shown that our semi-empirical tight-binding code is sufficiently accurate to calculate diffusion barriers on the surface, while being efficient enough to be used in large simulations, such as that of the interaction of hydrogen with step edges. The behaviour of hydrogen has been investigated for diffusion along dimer rows, from one end of a dimer to the other, across dimer rows, down steps and away from a defect, with good agreement being found between measured and modelled diffusion barriers. We can now give a full account of the behaviour of hydrogen on the Si(001) surface.

Leakage Current Distribution of Cu-Contaminated Thin SiO2

Dielectric degradation of an intentionally Cu-contaminated SiO2 film on an Si substrate was investigated using conducting atomic force microscopy. It was shown that local oxide leakage current did not increase at points occupied by Cu particles, while it increased at points other than that occupied by Cu particles. Combination of sulfuric acid/hydrogen peroxide mixture immersion and total reflection X-ray fluorescence analyses indicated that high-density Cu atoms near the SiO2 surface induced the high leakage current.

Selective Growth of Cu Nanowires on Si(111) Substrates

We succeeded in the fabrication of high-aspect-ratio (length to width) Cu nanowires of less than 10 nm width and 0.5 nm height along atomic step edge lines on Si(111) substrate. The fabrication procedure consisted of two wet process steps: (1) flattening of the surface roughness to an atomic level by immersing Si(111) wafers in ultralow-dissolved-oxygen water (LOW) and (2) Cu nanowire formation by immersion in LOW containing 100 ppb Cu ions for 100 s at room temperature. The selective growth of the Cu nanowires at the step edges indicates that Cu adsorption sites could be formed there during the flattening stage.

Structural Analysis of Bismuth Nanowire by X-Ray Standing Wave Method

Bismuth forms perfect atomic wires without any defects on a clean Si(001) surface. Despite the importance of this self-organized nanowire from the viewpoints of both surface science and device application, an analysis of the internal structure of the wire is quite difficult under the condition of a buried interface. In order to clarify the atomic structure of the wire capped by amorphous Si layers, the three-dimensional bismuth atomic site was measured with respect to the substrate Si lattice by the X-ray standing wave method. The results indicate that the absolute height of Bi atoms is 0.26 A upper from the bulklike Si(004) plane of the Si-dimer layer. For the structure inside the (004) plane, Bi atoms are in the range of ±0.5 A in the [110] direction from an intact Si-dimer position. This result disagrees with recent reports that were derived from other analytical methods used solely for a clean surface. A new model was proposed and it suggests an influence of a burying effect for the wire structure.

A probe-positioning method with two-dimensional calibration pattern for micro-multi-point probes

A probe-positioning method for micro-multi-point probes that can be independently driven is proposed. By the electron-beam lithography technique, we fabricated a 0.5 mm×0.5 mm-sized probe-positioning pattern matrix consisting of 750 nm×750 nm-sized cells. Each cell has 150 nm×150 nm-sized pits that represent a bit array, which specifies its address. Reading the address information on the pattern with the microprobes allowed us not only to determine the probe positions, but also to calibrate the orientation and dimension of each scan.

Short range and long range strain fields of Bi nanoline

Abstract The practical realisation of nanoscale devices requires the development of practical nanofabrication techniques. The Bi nanolines which self-assemble on Si(001) are promising templates for atomic scale wires, and also have a fascinating subsurface reconstruction. Elastic interactions are often responsible for the limited dimensionality of epitaxial nanoscale structures. The present work examines the elastic strain field around the Bi nanoline in terms of its interaction with other surface features. A short range tensile strain around the Bi nanoline may be identified by the effect on the electronic structure of the neighbouring dimers. A longer range elastic interaction is exhibited in a repulsive interaction between the nanoline and defects and steps. Atomic resolution variable bias scanning tunnelling microscopy (STM) and first principles electronic structure calculations have been used to elucidate these effects, and excellent agreement has been found between experimental observations and theoretical results.

Leakage Current Distribution and Dielectric Breakdown of Cu-Contaminated Thin SiO2

Dielectric degradation of an intentionally Cu-contaminated SiO 2 film on a Si substrate was investigated using conducting atomic force microscopy and metal-oxide-semiconductor capacitors Comparison of the results of both measurements clarified that local oxide leakage currents increased at random points except at the Cu particles. At the Cu particles, accelerated thermal oxidation leads to the formation of a thick SiO 2 layer at the interface with the Si substrate and suppression of the oxide leakage current. A combination of electrical evaluations and total reflection X-ray fluorescence analyses indicated that a high Cu concentration on a SiO 2 surface induced low-voltage dielectric breakdown, and a low Cu concentration inside the SiO 2 film induced high leakage current in a low electric field range.