Kikuo Yamabe

Time-dependent-dielectric breakdown of thin thermally grown SiO 2 films

To evaluate the reliability of thin thermally grown oxide films, we investigated both step stress breakdown and time-dependent dielectric breakdown (TDDB) which exhibited two distinguished slopes in Weibull plots. It is demonstrated that the intermediate breakdown mode (Bmode) in the breakdown histogram corresponded to the steep slope in the short time range of the TDDB plot. The steep slope is observed in the shorter time range with stress field and temperature. The electric field acceleration factor decreases with decreasing the oxide thickness. The TDDB data give us minimum voltage in the step stress breakdown histogram necessary to guarantee the device operation for 10 years. Comparison between the breakdown histogram and the minimum voltage indicates that theBmode defect should be decreased. Major origins of theBmode defect are oxygen microprecipitates and metallic contamination in the Si substrates. We found that both high-temperature preoxidation annealing and phosphorus diffusion into the back side of wafers greatly increase time to failure of thin thermally grown SiO2films because of decreasing both the number of oxygen microprecipitates and metallic contamination level.

Nonplanar oxidation and reduction of oxide leakage currents at silicon corners by rounding-off oxidation

We report that, based on the curvature radius at the convex corner of a trenched Si surface and electric field intensification, sacrificial thermal oxidation before gate oxide formation is very effective to round off the convex corner. We call it a rounding-off oxidation. From a simple one-dimensional model that considers both stress generation during Si oxidation and Stress relaxation by oxide viscous flow, it is foreseen that oxidation in a diluted oxidizing ambient and/or at a higher oxidation temperature reduces the stress in the oxide films. Experimentally, we report that the rounding-off oxidation with the above condition effectively rounds off the convex Si corner and decreases the thin gate oxide leakage currents and that the addition of a few percent of H2O to the dry oxygen rounding,off oxidation ambient is also effective. The relation between the sacrificial rounding-off oxidation and the time-dependent dielectric breakdown of thin gate oxides formed at the convex corner is also shown.

Electrical characteristics of rapid thermal nitrided-oxide gate n- and p-MOSFET's with less than 1 atom% nitrogen concentration

The characteristics and reliability of nitrided-oxide gate n- and p-MOSFETs with less than 1 atom% nitrogen concentration in the gate films were investigated in detail. These very light nitridations were accomplished using NH/sub 3/ gas at low temperatures/spl minus/from 800/spl deg/ C to 900/spl deg/ C. Nitrogen concentrations as low as 0.13 atom% were successfully measured by SIMS and AES. The region of optimum nitrogen concentration for deep-submicron devices is discussed. We explain how good drivability and good hot-carrier reliability were attained simultaneously with a nitrogen concentration of around 0.5 atom%, which is equivalent to that of oxynitride gate MOSFETs using N/sub 2/O gas. The suppression of boron penetration is also discussed. Light nitridation by ammonia gas is particularly desirable for deep-submicron processes because it can be accomplished at a relatively low temperature of about 900/spl deg/C. >

Effects of boron penetration and resultant limitations in ultra thin pure-oxide and nitrided-oxide gate-films

The boron penetration effect was compared for p/sup +/ poly gate PMOSFETs with pure oxide gates and nitrided oxide gates. For a gate thickness of 6.5 nm, reduced boron dosage and rapid thermal processing solve the problem of boron penetration in the pure oxide case. However, when the film thickness is less than 6.5 nm, only a nitrided oxide film can solve the problem. From the results of EDX analysis in nitrided oxide films, it was found that nitrogen build-up at the interface is small and that a nitrogen concentration of only a few percent leads to complete suppression of boron penetration down to the 2 nm range of film thickness. Excellent characteristics in 2.6 nm nitrided oxide gate p-MOSFETs, free from boron penetration effects, were demonstrated.<<ETX>>

Very lightly nitrided oxide gate MOSFETs for deep-sub-micron CMOS devices

The characteristics and reliability of the nitrided oxide gate n- and p-MOSFETs with less than 1 atom% nitrogen concentration gate films were investigated in detail. These very light nitridations were accomplished using NH/sub 3/ gas at low temperatures from 800 degrees C to 900 degrees C. The low nitrogen concentrations, such as 0.13 atom% were obtained by SIMS and AES (Auger electron spectroscopy) measurements. The optimum nitrogen concentration region for the deep-sub-micron device is discussed. It was shown that, with the 0.5 atom% nitrogen concentration, good drivability and good hot carrier reliability were attained at the same time, and they were equivalent to those of the oxynitride gate MOSFETs using N/sub 2/O gas. The suppression of boron penetration is also discussed.<<ETX>>

Depth profiling of Si-SiO2 interface structures

The Si-SiO2 interface structures of thermally grown oxide films on (100) surfaces were studied using three types of depth profiling measurement. Analysis of these measurements confirms the interface structures determined previously by nondestructive depth profiling.1) The appicability of chemical depth profiling to the study of interface structures was also studied. A new method of spectral analysis, used successfully in the present measurements, is presented.

Relationship between mobility and residual-mechanical-stress as measured by Raman spectroscopy for nitrided-oxide-gate MOSFETs

The cause of unusual transconductance behavior in MISFETs with nitrided oxide gate insulator films was studied. In particular, the effect of mechanical stress induced by nitrided-oxide films on the transconductance was investigated. The residual mechanical stress in nitrided oxide films was evaluated by Raman spectroscopy and by two-dimensional mechanical stress simulation. It was found that, with higher interfacial nitrogen concentration, the tensile stress rises at the silicon and the gate insulator interface. The transconductance dependence on the mechanical stress was measured by deforming the wafer. All the results suggest that residual tensile stress is one of the causes of the transconductance behavior.<<ETX>>

Hot carrier related phenomena for n- and p-MOSFETs with nitrided gate oxide by RTP

The electric characteristics of nitrided gate oxide n- and p-MOSFETs were investigated. In particular, hot carrier induced degradation was studied in detail. It was confirmed that the nitrided gate oxide samples are resistive to interface state generation for both the n- and p-MOSFET cases. However, the hot electron trapping of the nitrided p-MOSFET was found to be larger than that of a pure gate oxide device. Relations between the degradations and substrate and gate currents were investigated. Other characteristics, such as mobility and the snap-back phenomenon, were also compared between the nitrided and pure oxide devices. It was found that nitrided gate oxide n-MOSFET mobilities are improved under high gate bias. On the other hand, nitrided oxide p-MOSFET mobilities are degraded. The snap-back breakdown voltages of the nitrided oxide devices were found to be improved for both n- and p-channel cases.<<ETX>>

Si-SiO2 interface structures: chemical shifts in Si 2p photoelectron spectra

From XPS depth profiling of silicon oxide films formed on (100), (110) and (111) surfaces prepared by various oxidation processes, the effect of crystallographic orientation on the chemical shift was found, and the effects of oxidation temperature, oxidation atmosphere and annealing on the chemical shifts were found to be small. These results imply that chemical shifts are weakly affected by the change in the Si-O-Si bond angle near the Si-SiO2 interface.

Process technologies for high density, high speed 16 megabit dynamic RAM

This paper describes key points of submicron CMOS technologies for an experimental 16 Mbit DRAM fabrication. The memory cell and the transistor designs are most important to realize high density, high speed DRAMs. The main features of the technology are a new buried stacked capacitor cell and a high speed CMOS structure. The lithographic levels used were 0.7 µm for critical layers. The technologies have been verified using test vehicles and experimental 16 Mbit DRAM.