Toshiyuki Tsutsumi

Cross-Sectional Channel Shape Dependence of Short-Channel Effects in Fin-Type Double-Gate Metal Oxide Semiconductor Field-Effect Transistors

The dependence of short-channel effects (SCEs) on the cross-sectional channel shape of the fin-type double-gate metal oxide semiconductor field-effect transistors (MOSFETs) has been experimentally investigated from the viewpoint of fin fabrication. The three types of fin-type double-gate MOSFETs (FinFETs) with a rectangular-cross-section channel on a (110)-oriented silicon-on-insulator (SOI) wafer, and a triangular and trapezoidal channels on a (100)-oriented SOI wafer were fabricated using the same orientation-dependent wet etching process. The experimental results show that the SCEs in rectangular-cross-section silicon (Si)-fin channel devices are well suppressed compared with those in a triangular or a trapezoidal Si-fin channel device fabricated using a similar mask pattern, in the regimes of the gate length of less than 85 nm and Si fin height of larger than 65 nm. The presented experimental results are valuable for FinFET design and fabrication.

Fin-Type Double-Gate Metal-Oxide-Semiconductor Field-Effect Transistors Fabricated by Orientation-Dependent Etching and Electron Beam Lithography

We present the Fin-type double-gate metal-oxide-semiconductor field-effect transistors (FXMOSFETs, the XMOS transistor was named because its cross section resembles the Greek letter Ξ which corresponds to the English letter X) with ideal rectangular fin cross section, for the first time, using (110)-oriented silicon-on-insulator (SOI) wafers. The nanoscale silicon (Si)-Fin has successfully been fabricated by orientation-dependent etching using an etchant of 2.38% tetramethylammonium hydroxide (TMAH) solution. The almost ideal subthreshold slope of 64 mV/decade was obtained for the fabricated 20 nanometers (nm) Si-Fin and 145 nm gate length FXMOSFET. This excellent subthreshold characteristic experimentally shows that the interface property of the Si-Fin channel with (111)-oriented sidewalls is suitable to realize a high-performance FXMOSFET. The electrical characteristics of the fabricated FXMOSFETs in the 20–100 nm Si-Fin width regime have been systematically investigated. The experimental results indicate that the short-channel effects (SCEs) can be effectively suppressed by reducing the Si-Fin width to 20 nm or less. The developed processes are promising for fabrication of the FXMOSFET as a future nano-silicon device.

Clues for Modeling and Diagnosing Open Faults with Considering Adjacent Lines

Under the modern manufacturing technologies, the open defect is one of the significant issues to maintain the reliability of DSM circuits. However, the modeling and techniques for test and diagnosis for open faults have not been established yet. In this paper, we give an important clue for modeling an open fault with considering the affects of adjacent lines. Firstly, we use computer simulations to analyze the defective behaviors of a line with the open defect. From the simulation results, we propose a new open fault model that is excited depending on the logic values at the adjacent lines assigned by a test. Next, we propose a diagnosis method that uses the pass/fail information to deduce the candidate open fault. Finally, experimental results show that the proposed method is able to diagnose the open faults with good resolution. It takes about 6 minutes to diagnose the open fault on the large circuit (2M gates).

Analysis of backscattering phenomenon from drain region in a silicon nanodiode

In this paper, the backscattering phenomenon from drain region in a silicon nanodiode was analyzed. A Monte Carlo simulation is employed for analyzing the backscattering effect in a short channel device.

Fully-functional FPGA prototype with fine-grain programmable body biasing

A fully-functional FPGA prototype chip in which the programmable body bias voltage can be individually applied to elemental circuits such as MUXes, LUT and DFF is fabricated using low-power 90-nm bulk CMOS technology and the area overhead, dynamic current, static current and operational speed are evaluated in silicon. In measurements, 10 ISCAS benchmark circuits are implemented by employing newly developed CAD tools which consist of VT mapper as well as placer and router. Mask layout shows that well-separated margins, programmable body bias circuits, and additional configuration memories occupy 54% of the FPGA tile area. Measurement results show that the fabricated FPGA reduces the static current by 91.4% in average. In addition, evaluations by implementing ring oscillator with various body bias voltage pairs demonstrate the static current reduction from 23.1 uA to 1.0 uA by assigning low threshold voltage and high threshold voltage to MOSFETs on a critical path and the rest of the MOSFETs, respectively while maintaining the same oscillation frequency of 6.6 MHz as the frequency when all MOSFETs are assigned low threshold voltage. Moreover the fine-grain programmable body bias technique accelerates the oscillation frequency of ring oscillator implemented on FPGA by aggressively applying forward body bias voltage, while assignment of HVT to MOSFETs on the non-critical path by applying the reverse body biasing effectively suppresses exponential increase of static current caused by the forward body biasing.

A Novel Approach for Improving the Quality of Open Fault Diagnosis

With the shrinking process technologies and the use of copper process, open defects on interconnect wires, contacts and vias often cause failure. Development of an efficient fault diagnosis method for open faults is desired. However, the diagnosis method for open faults has not been established yet. In this paper, we propose a novel approach for improving the diagnostic quality of open faults by introducing a threshold function in which the logical value of the line with open defect depends on the weighted logical values of its adjacent lines. By using the threshold function, we can deduce not only a faulty line but also an open defect site at the faulty line. Experimental results show that the proposed method can identify an exact faulty line in most cases with a very small computation cost. The proposed method can also identify the open defect site within 25%-length of the faulty line.

Fault Effect of Open Faults Considering Adjacent Signal Lines in a 90 nm IC

Open faults are difficult to test since the voltage at the floating line is unpredicted and depends on the voltage at the adjacent lines. The modeling for open faults with considering adjacent lines has been proposed in [10]. In this work, the 90 nm IC is designed and fabricated to evaluate how the voltage at adjacent lines affect the defective line. The open fault macros with a transmission gate and with an intentional break are included in the IC. The nine lines are placed in parallel in three layers to observe the effect of the coupling capacitance when an open occurs. The benchmark circuits with the open fault macro are also included in the IC. The simulation and experimental results show that the relationship between the floating line and the adjacent lines. The experimental results are also compared withxa0xa0the open fault model that calculate the weighted sum of voltages at the adjacent lines.

Test Generation and Diagnostic Test Generation for Open Faults with Considering Adjacent Lines

In order to ensure high quality of DSM circuits, testing for the open defect in the circuits is necessary. However, the modeling and techniques for test generation for open faults have not been established yet. In this paper, we propose a method for generating tests and diagnostic tests based on a new open fault model. Firstly, we show a new open fault model with considering adjacent lines [9]. Under the open fault model, we reveal more about the conditions to excite the open fault. Next we propose a method for generating tests for open faults by using a stuck-at fault test with dont cares. We also propose a method for generating a diagnostic test that can distinguish the pair of open faults. Finally, experimental results show that (1) the proposed method is able to achieve 100% fault coverages for almost all benchmark circuits and (2) the proposed method is able to reduce the number of indistinguished open fault pairs.

A method for diagnosing resistive open faults with considering adjacent lines

It is believed that resistive open faults can cause small delay defects at wires, contacts, and/or vias of a circuit. However, it remains to be elucidated whether any methods could diagnose resistive open faults. We propose a method for diagnosing resistive open faults by using a diagnostic delay fault simulation with the minimum detectable delay fault size. We also introduce a fault excitation function for the resistive open fault to improve the accuracy of the diagnostic result. The fault excitation function for the resistive open fault can determine a size of an additional delay at a faulty line with considering the effect of the adjacent lines. We demonstrated that the proposed method is capable of identifying fault locations for the resistive open fault with a small computation cost.

Evaluation of granularity on threshold voltage control in flex power FPGA

The flex power FPGA can flexibly control speed and power in a trade-off relationship by a flexible assignment of proper threshold voltage generated from body-bias units to transistors. This paper evaluates static power consumption and an area-overhead by the body-bias units on various threshold voltage control granularity in the flex power FPGA. There is also a trade-off relationship between the static power consumption and the area-overhead for granular control of the threshold voltages. Both a grain size and its style of division have a strong influence on the trade-off. Own evaluation results show that static power reduces less than 1/5 of original level, while increase an area overhead of less than 40%. If an area increase of 50% is allowed, then the reduction in static power consumption to 1/10 or less is obtained