Kazuya Tanigawa

Exploring compact design on high throughput coarse grained reconfigurable architectures

Aiming toward a compact high- throughput reconfigurable architecture, we propose the reconfigurable processor DS-HIE. In order to achieve the characteristics of compactness and high-throughput, the DS-HIE architecture executes operations following a bit-serial computation scheme and adopts a Benes network as its routing resource. Implementing bit-serial computation brings the advantage of small chip area and high throughput to the DS-HIE architecture, and the Benes network ensures the high availability of the routing paths within a compact chip area. In this paper, we explain several methods, namely two data transfer methods and three feedback path methods, and provide an evaluation of the architecture. The evaluation results showed that the structure which allows for the smallest chip area comprises the dedicated wiring method for data transfer and the area effort method for routing. Further, the transistor count of the DS-HIE processor is notably smaller than that of the core 2 duo processor.

Design of superscalar processor with multi-bank register file

Recently, register files in highly parallel superscalar processors tend to have large chip areas and many access ports. This trend causes problems with chip-size, access time and power consumption. As one of the methods for solving these problems, we have proposed a multi-bank register file which realizes small area, high speed and low power consumption. We have proved the effectiveness of this method by simulation. We now show a detailed design of a superscalar processor with a multi-bank register file and its evaluation results. From the design by Verilog-HDL, the processor with the multi-bank register file improves register access speed by 49% at the cost of 28% more gates for register-access scheduling. These results verify that we have solved the problem of shortening the critical path around the register file in highly parallel processors.

A Generalized Execution Model for Programming on Reconfigurable Architectures and an Architecture Supporting the Model

In this paper, we consider the possibility of using a reconfigurable architecture as a general-purpose computer. Many reconfigurable architectures have been proposed. However, these architectures are hard to use as a general-purpose computer because their architectures have no explicit execution model for software developments. Therefore, in this paper, we propose an Ideal PARallel Structure (I-PARS) execution model. To make software developments easily, the program based on the I-PARS execution model has no limitation depending on the hardware structure of the processor based on any reconfigurable architectures. Also, we propose a PARS architecture to execute programs based on the I-PARS execution model effectively. Further, we implement a prototype processor based on the PARS architecture and estimated its performance. From the implementation and the estimation, we show the feasibility of programming on the I-PARS execution model and executing it on the PARS architecture.

Multi-Bank Register File for Increased Performance of Highly-Parallel Processors

A multi-bank register file architecture for increasing the register-access clock frequency by up to 95 % and an access arbitration method for avoiding degradation of the cycle number based processor performance are reported. A 4-bank test design in 200 nm gate-length CMOS with 12 ports and 128 registers has 0.39 mm2 area and operates at up to 417 MHz

A coarse-grained reconfigurable architecture with low cost configuration data compression mechanism

In our research, we propose a PARS architecture as a reconfigurable architecture for general purpose. Reconfigurable architectures including the PARS architecture have a serious issue as its configuration data size becomes huge. In case of coarse-grained reconfigurable architectures, the issue is less serious compared with the fine-grained reconfigurable architectures. However, if the unused region on reconfigurable hardware is large, its configuration data includes much invalid information. In this paper, to ease the issue, we have designed a reconfigurable processor which enables to compress valid operations in several successive configuration data into one configuration data and execute it. From the chip design of the processor, the mechanism increases the number of transistor to only 0.17%, and it reduces the size of configuration data for a FEAL cipher program to 28% of the original configuration data size.

Superscalar processor with multi-bank register file

Register files in highly parallel superscalar processors tend to have large chip area and many access ports. This trend causes problems with chip-size, access time and power consumption. As one of the methods for solving these problems, we have proposed a multi-bank register file which realizes small area, high speed and low power consumption. We have proved effectiveness of this method by software simulation, and by detail designing it as synthesizable Verilog-HDL description with a full custom designed multi-bank register file. In this paper, we show the detail architecture of a superscalar processor with the multi-bank register file and its evaluation results.

A PLD Architecture for High Performance Computing

In recent years, Field Programmable Gate Arrays (FPGAs) have been used for High Performance Computing (HPC). Because there is a significantly difference between configuration speed of FPGA and execution speed of Central Processing Unit (CPU), the difference causes performance degradation. To resolve of this problem, we proposed MPLD as a new Programmable Logic Device (PLD) architecture with high speed reconfiguration. The merits of the MPLD in HPC are high speed configuration and easy partial configuration.This is achieved by the configuration method which is same as write memory access of conventional parallel memory. In this paper, we describe the problems of FPGA on using it in HPC, and present the MPLD architecture which solves the problems. Some evaluation results of the prototype MPLD chip which implemented by using five metal layers ROHM 0.18¿m CMOS technology are also presented. As results, memory capacity of the prototype MPLD was 49152bit, and the core area was 1767.54 × 1690.96¿m2 and the number of metal layers used for wiring was three. The achieved configuration time is about 6.6¿sec for whole prototype MPLD. The configuration speed of the prototype MPLD is about 11.7 times higher than AS configuration used for Altera FPGAs.

Evaluation of compact high-throughput reconfigurable architecture based on bit-serial computation

In this paper, aiming toward a compact high-throughput reconfigurable architecture, we propose the reconfigurable processor DS-HIE. In order to achieve the characteristics of compactness and high-throughput, the DS-HIE architecture executes operations following a bit-serial computation scheme and adopts a Benes network as its routing resource. Implementing bit-serial computation brings the advantage of small chip area and high throughput to the DS-HIE architecture, and the Benes network ensures the high availability of the routing paths within a compact chip area. In this paper, we evaluated its transistor count and performance, compared with the RISC processor MeP. From this evaluation, the DS-HIE processor required 9.2 times the transistor count of the MeP processor, it achieved 13 to 33 times higher performance as compared with the MeP processor.

EDA Environment for Evaluating a New Switch-Block-Free Reconfigurable Architecture

In this study, we developed and implemented a placement and routing algorithm for a new switch-block-free fine-grain reconfigurable device, called MPLD, as an evaluation environment of MPLDs ability to realize sequential circuits. An MPLD consists of an array of multiple-output LUTs (MLUTs), which work as logic elements and/or routing elements, and has no switch blocks for routing, unlike FPGAs. Thus, when the logic cells of a circuit are placed on an MPLD, MLUTs need to be reserved for routing around the placed logic cells. Our simulated annealing-based placement algorithm for MPLDs avoids overcrowding logic cells and reserves routing space, by considering (1) detailed estimated wire congestion and (2) distance between logic cells, in its cost function. In experiments, we confirmed that sequential circuits were successfully placed and routed on MPLDs in our evaluation environment.

Design consideration for reconfigurable processor DS-HIE — Trade-off between performance and chip area

To develop a new processor for embedded applications, we must first characterize the processor, in order to take appropriate trade-off between performance and chip area. This study presents a DS-HIE architecture, which achieve high performance on a limited chip area by using the appropriate bit-width.