Koh Johguchi

x11 performance increase, x6.9 endurance enhancement, 93% energy reduction of 3D TSV-integrated hybrid ReRAM/MLC NAND SSDs by data fragmentation suppression

A 3D through-silicon-via (TSV) -integrated hybrid ReRAM/multi-level-cell (MLC) NAND solid-state drives (SSDs) architecture is proposed for PC, server and smart phone applications. NAND-like interface (I/F) and sector-access overwrite policy are proposed for the ReRAM. Furthermore, intelligent data management algorithms are proposed. The proposed algorithms suppress data fragmentation and excess usage of the MLC NAND by storing hot data in the ReRAM. As a result, 11 times performance increase, 6.9 times endurance enhancement and 93% write energy reduction are achieved compared with the conventional MLC NAND SSD. Both ReRAM write and read latency should be less than 3μs to obtain these improvements. The required endurance for ReRAM is 105. 3D TSV interconnects reduce the energy consumption by 68%.

HiSIM-HV: A Compact Model for Simulation of High-Voltage MOSFET Circuits

The completely surface-potential-based MOSFET model HiSIM-HV for high-voltage applications of up to several hundred volts is reviewed, and recently developed new model capabilities are presented. HiSIM-HV enables a consistent evaluation of current and capacitance characteristics for symmetric and asymmetric high-voltage MOSFETs due to a consistent description of the potential distribution across the MOSFET channel as well as the resistive drift regions. The anomalous features, often observed in the capacitances, are explained by large potential drops in the drift regions. Accurate modeling of the overlap region between the gate and drift region is also demonstrated. Different device features based on different device structures are well explained by the geometrical differences.

A High Performance and Energy-Efficient Cold Data Eviction Algorithm for 3D-TSV Hybrid ReRAM/MLC NAND SSD

A hybrid 3D-TSV ReRAM/MLC NAND SSD with cold data eviction (CDE) algorithm is proposed. In the proposed hybrid SSD, the lifetime and energy consumption are dominated by MLC NAND flash memory due to ReRAMs high endurance and low power consumption. In addition, partial page overwrites are possible in ReRAM. Thus, the write accesses to MLC NAND flash memory are largely reduced by storing hot data in ReRAM. As a result, the SSD energy consumption decreases and the lifetime is prolonged. With the CDE algorithm, a page-level adaptive data migration is achieved, which is transparent to the file system. Compared to the previous work, 8-times write throughput increase, 83% energy reduction and 6.5-times longer longevity are achieved with 3D-TSV technology. Moreover, from the experimental results, the data eviction should be triggered when ReRAM free space ratio decreases to a range of 8%-20%. Hence, the eviction frequency is adaptive to the data pattern in the hybrid SSD. The experimental results also suggest the requirements for ReRAM. To obtain the best effect, both the read and write latency of ReRAM should be below 3 μs for 512 Bytes.

SCM capacity and NAND over-provisioning requirements for SCM/NAND flash hybrid enterprise SSD

The required storage class memory (SCM) capacity and NAND over-provisioning (OP) for SCM/NAND hybrid enterprise solid state drive (SSD) are evaluated for various storage workloads. From the worst case simulations (hot and random data intensive workloads), it is found that less than 8% SCM/NAND capacity ratio with below 25% NAND OP is sufficient assuming SCM bit cost is 10-times as high as that of NAND. Other workloads with the exception of all-cold-data case can use less than 4% SCM/NAND capacity ratio with 100% NAND OP. According to the analyses, SCM tends to be cost-effective for the hot workload rather than the random one. Furthermore, the effect of NAND organization on the hybrid SSD write performance is considered. NAND organization with an 8-128KB page size and 1-8MB block size provides the best performance for the hot and random data intensive workloads. From the energy point of view, SCM/NAND hybrid SSD allows larger NAND page sizes compared with NAND-only SSD.

Through-Silicon Via Design for a 3-D Solid-State Drive System With Boost Converter in a Package

A 3-D solid-state drive system with through-silicon via (TSV) technology and boost converter is presented in this paper. The proposed boost converter enables the supply voltage reduction to 1.8 V and smaller NAND Flash memory chips. From the simulation results, the conventional bonding-wire technology can achieve only eight NAND chip integrations not only due to their structural problem but also due to the performance degradation. On the other hand, 128 NAND Flash memory chips can be integrated into a package with full-copper TSVs and the proposed system has about 1.70 μs of rise time for 20 V, 74.2 nJ of the energy dissipation, and 225 μm2 of additional Si area consumption for a NAND chip. Even if poly-Si TSVs are used, because of the process restriction, 64 NAND chips can be stacked with about 34% longer rise time and 22% degradation of energy dissipation compared to a full-copper TSV by grinding the Si-substrate to 10 μm .

A workload-aware-design of 3D-NAND flash memory for enterprise SSDs

Solid-state drives (SSDs) have a growing trend of replacing hard disk drives (HDDs) in large computing systems to meet the requirements of power and space. Data in SSD are stored in NAND flash memory cells. Since 2-dimensional (2D) scaling is facing various limitations, 3D-NAND flash memory architectures have been proposed to maintain the trend of bit density increase and bit cost reduction, which prefers large block sizes and page sizes. However, overly large block and page sizes flash memory harm the throughput of NAND flash devices. The actual page size and block size of the NAND flash memory product are as small as 8KB and 2MB respectively to avoid the performance degradation. Alternatively, emerging nonvolatile memory devices named storage class memories (SCMs) feature in high speed, low power consumption and high endurance. By combining SCM, large block sizes and page sizes, required especially for the 3D-NAND flash device case, are acceptable for SCM/NAND flash hybrid SSD. In this paper, a workload-aware NAND organization design is investigated for enhancing the performance of both SSD with only NAND flash memory and SCM/NAND flash hybrid SSD. From the experimental results, a 16MB NAND block size that corresponds to 512 layers and 16KB page size in a 512Gbit P-BiCS 3D-NAND flash memory can be acceptable for applications like relational database and financial online transaction processing. Additionally, a large NAND flash page size of 512KB is also acceptable for the firewall/web proxy, relational database and project directories applications. With SCM, the acceptable page and block sizes of the 3D-NAND flash memory can be magnified up to 64-times and 4-times, respectively, compared with the conventional SSD composed of only NAND flash memory.

Measurement-Based Ring Oscillator Variation Analysis

As transistor size scales down, unavoidable process variations are rapidly increasing. Consequently, its essential for designers to accurately estimate within-die and interdie variations so that circuits and integrated systems can operate correctly. This article describes an analysis of ring oscillators that were designed in 180-nm and 100-nm CMOS technologies, and discusses the oscillators frequency variations as determined for different stage numbers and supply voltages.

Correlating Microscopic and Macroscopic Variation With Surface-Potential Compact Model

Variation analysis of n-MOSFETs fabricated by different manufacturers at three technology nodes (180, 100, and 65 nm) demonstrates that surface-potential compact models are capable to bridge the gap between circuit simulation and TCAD by enabling extraction of microscopic MOSFET-parameter variation from measured macroscopic Vth and Ion variations. Considering only the four microscopic variations of substrate doping, pocket-implantation doping, carrier mobility degradation due to gate-interface roughness, and channel-length change, is found sufficient to reproduce within-wafer Vth and Ion variations of wide MOSFETs (Wg = 10 mum) for all Lg and all three technology nodes. Extracted microscopic variation reductions between 180- and 65-nm nodes range from 25% for pocket doping to 70% for carrier mobility degradation. However, Vth and Ion variations at shortest Lg remain approximately constant for all three technologies, in spite of the substantial variation reductions at the microscopic level.

Investigation and Improvement of Verify-Program in Carbon Nanotube-Based Nonvolatile Memory

Carbon nanotube (CNT)-based random access memory (NRAM) cells are measured to investigate cell program at different set current compliances and temperatures. Then, a physical model is proposed to explain the mechanism of cell resistance switching. Specifically, the changes in the NRAM cell tunneling current and resistance can be attributed to the variation of the distance between CNTs. An attraction force (Fattraction), generated by electrical induction, reduces the distance, whereas a repulsion force (Frepulsion), generated by phonon-induced temperature, increases the distance. It is proposed that the dominance of these two forces is reversed during set and reset programs, possibly due to the reduction of Frepulsion in set program. Finally, two verify-reset schemes are proposed to improve the NRAM cell verify-program performance. The first proposal, multiple-pulse reset demonstrates 23% program time reduction by skipping a cell resistance read between two successive reset pulses. The second proposal, gate-pulse reset is calculated to decrease more than 40% program energy by reducing bitline charge energy in array program.

Investigation of multi-level-cell and SET operations on super-lattice phase change memories

This paper gives the optimum SET pulse with the investigation on SET current delay and the multi-level-cell (MLC) operation for super-lattice phase change memories (SL-PCMs). From the investigation, the voltage, or the electric field triggers RESET/SET transition of SL-PCM. The induced energy is also essential for changing the resistance state. In this paper, the MLC operation is also verified with RESET pulse, 1-step SET pulse and 2-step SET pulse. The measurement results indicate the 2-step SET pulse is the best for the MLC function, which realizes the precise resistance controlling. Additionally, the retention-time is measured to evaluate the reliability of MLC SL-PCM. The features of SL-PCM are not only small RESET/SET current, but also MLC operation and the SL-PCM technology provides a potential for next generation non-volatile memories.