Tetsuo Hironaka

Evaluation of low-energy and high-performance processor using variable stages pipeline technique

A methodology for low-energy and high-performance computing that is essential in mobile and ubiquitous computing is proposed. The dynamic voltage scaling (DVS) is one of the current major methodologies for low-power devices. However by DVS, the lower the chip voltage becomes in the future, the less energy saving is obtained by DVS. Therefore in order to reduce the energy consumption for lower voltage devices, variable stages pipeline (VSP) processor with the latch D-FF selector (LDS)-cell that unifies pipeline stages dynamically and also decreases energy consumption caused by glitch propagations on a low- energy mode is proposed. With its features, the VSP technique can achieve low-energy computing without any dependence on chip voltage. It is shown that the VSP processor can achieve low-energy computing and higher performance computing than the DVS processor in the low-energy mode by evaluating the proposed approach using SpeclNT2000 benchmark suite.

Exploring compact design on high throughput coarse grained reconfigurable architectures

Aiming toward a compact high- throughput reconfigurable architecture, we propose the reconfigurable processor DS-HIE. In order to achieve the characteristics of compactness and high-throughput, the DS-HIE architecture executes operations following a bit-serial computation scheme and adopts a Benes network as its routing resource. Implementing bit-serial computation brings the advantage of small chip area and high throughput to the DS-HIE architecture, and the Benes network ensures the high availability of the routing paths within a compact chip area. In this paper, we explain several methods, namely two data transfer methods and three feedback path methods, and provide an evaluation of the architecture. The evaluation results showed that the structure which allows for the smallest chip area comprises the dedicated wiring method for data transfer and the area effort method for routing. Further, the transistor count of the DS-HIE processor is notably smaller than that of the core 2 duo processor.

A novel hierarchical multi-port cache

A novel hierarchical multi-port cache is described in this paper, which implements the hierarchical multi-port memory architecture (HMA) based on 1-port banks. This type of cache has the advantages of high access bandwidth, low power dissipation and small area, which are studied and explained in detail. A test chip design of a 4-port HMA cache with 0.18/spl mu/m CMOS technology has been made.

Design of superscalar processor with multi-bank register file

Recently, register files in highly parallel superscalar processors tend to have large chip areas and many access ports. This trend causes problems with chip-size, access time and power consumption. As one of the methods for solving these problems, we have proposed a multi-bank register file which realizes small area, high speed and low power consumption. We have proved the effectiveness of this method by simulation. We now show a detailed design of a superscalar processor with a multi-bank register file and its evaluation results. From the design by Verilog-HDL, the processor with the multi-bank register file improves register access speed by 49% at the cost of 28% more gates for register-access scheduling. These results verify that we have solved the problem of shortening the critical path around the register file in highly parallel processors.

A Generalized Execution Model for Programming on Reconfigurable Architectures and an Architecture Supporting the Model

In this paper, we consider the possibility of using a reconfigurable architecture as a general-purpose computer. Many reconfigurable architectures have been proposed. However, these architectures are hard to use as a general-purpose computer because their architectures have no explicit execution model for software developments. Therefore, in this paper, we propose an Ideal PARallel Structure (I-PARS) execution model. To make software developments easily, the program based on the I-PARS execution model has no limitation depending on the hardware structure of the processor based on any reconfigurable architectures. Also, we propose a PARS architecture to execute programs based on the I-PARS execution model effectively. Further, we implement a prototype processor based on the PARS architecture and estimated its performance. From the implementation and the estimation, we show the feasibility of programming on the I-PARS execution model and executing it on the PARS architecture.

Multi-Bank Register File for Increased Performance of Highly-Parallel Processors

A multi-bank register file architecture for increasing the register-access clock frequency by up to 95 % and an access arbitration method for avoiding degradation of the cycle number based processor performance are reported. A 4-bank test design in 200 nm gate-length CMOS with 12 ports and 128 registers has 0.39 mm2 area and operates at up to 417 MHz

A coarse-grained reconfigurable architecture with low cost configuration data compression mechanism

In our research, we propose a PARS architecture as a reconfigurable architecture for general purpose. Reconfigurable architectures including the PARS architecture have a serious issue as its configuration data size becomes huge. In case of coarse-grained reconfigurable architectures, the issue is less serious compared with the fine-grained reconfigurable architectures. However, if the unused region on reconfigurable hardware is large, its configuration data includes much invalid information. In this paper, to ease the issue, we have designed a reconfigurable processor which enables to compress valid operations in several successive configuration data into one configuration data and execute it. From the chip design of the processor, the mechanism increases the number of transistor to only 0.17%, and it reduces the size of configuration data for a FEAL cipher program to 28% of the original configuration data size.

Superscalar processor with multi-bank register file

Register files in highly parallel superscalar processors tend to have large chip area and many access ports. This trend causes problems with chip-size, access time and power consumption. As one of the methods for solving these problems, we have proposed a multi-bank register file which realizes small area, high speed and low power consumption. We have proved effectiveness of this method by software simulation, and by detail designing it as synthesizable Verilog-HDL description with a full custom designed multi-bank register file. In this paper, we show the detail architecture of a superscalar processor with the multi-bank register file and its evaluation results.

Low power bank-based multi-port SRAM design due to bank standby mode

A low power multi-port SRAM design method based on banks switchable between active and standby mode is described. Speed decrease is prevented by use of an access method with hidden precharge-time. More than 56% power reduction can be achieved when 64 banks are used to implement a 4-port SRAM. A 4 kB SRAM with 4 ports and 16 banks has been designed and fabricated for verification.

Bank-Type Multiport Register File for Highly-Parallel Processors

Tetsuya Sueyoshi, Hiroshi Uchida, Yosuke Mitani, Ken Hiramatsu, Hans Jürgen Mattausch, Tetsushi Koide, and Tetsuo Hironaka Research Center for Nanodevices and Systems, Hiroshima University, 1-4-2 Kagamiyama, Higashi-Hiroshima,739-8527, Japan Graduate School of Information Sciences, Hiroshima City University, 3-4-1 Ozuka-Higashi, Asaminami-ku, 731-3194, Japan Phone: +81-824-24-6265 Fax: +81-824-22-7185 email: {sueyoshi,hjm,koide}@sxsys.hiroshima-u.ac.jp