Yukio Akazawa

Si bipolar 2-GHz 6-bit flash A/D conversion LSI

A gigahertz-sampling-rate flash A/D (analog/digital)-conversion LSI using high-speed Si bipolar technology (SST-1B) is investigated. To improve comparator speed, a circuit technology to minimize the comparator-speed limiting factors with minimum power is investigated and applied. To enhance the dynamic accuracy, speed mismatch among comparators is also minimized using this circuit technology. To improve encoder speed, a quasi-Gray code is adopted and glitch noise is reduced with this code. The LSI performance at 1-GHz sampling rate is measured with a gigahertz-operation data acquisition system developed with the SST MSI family, and effective bits of 5.8 at an input frequency of 100 MHz and 4.8 at 500 MHz are achieved. This LSI also demonstrates the feasibility of a single-chip flash A/D converter with a gigahertz sampling rate using Si bipolar technology. >

A 156-Mb/s CMOS optical receiver for burst-mode transmission

In a point-to-multipoint fiber-optic subscriber system using TDMA (time division multiple access), the receiver should be able to handle burst-data packets with different amplitudes, Moreover, high-bit-rate operation is desired for multimedia communications. The operational speed is mainly restricted by the input parasitic capacitance of the preamplifier. Reducing the input impedance of the preamplifier widens its frequency bandwidth, and it makes high-speed operation possible. A multistaged preamplifier using feedforward phase compensation technique has been devised for small input impedance with stable operation at high frequency. Multistaged feedforward bias control is used for quick response to burst data, and the time constant is also reduced for high-speed operation. Using these design techniques, an optical receiver IC was fabricated using standard 0.5-/spl mu/m CMOS technology. The instantaneous response receiver has high sensitivity of -35.6 dBm, a wide dynamic range of more than 26 dB for burst-mode optical input at 156 Mb/s, and requires no external adjustment. The use of standard CMOS technology and the freedom from external adjustment make it possible to build an inexpensive receiver module.

An instantaneous response CMOS optical receiver IC with wide dynamic range and extremely high sensitivity using feed-forward auto-bias adjustment

An instantaneous response CMOS optical-receiver IC is described with wide input dynamic range and high sensitivity. In a TCM (time compression multiplexing)-TDMA (time division multiple access) fiber-optic subscriber system, a receiver should be able to handle burst-data packets with different amplitude. This requires quick response and a wide dynamic range. Instantaneous response is achieved with a new feed-forward auto-bias adjustment technique. In addition, multistaged offset compensation provides a wide dynamic range without any external elements and adjustments. Using these design techniques, an optical receiver IC was fabricated in a standard 0.8-/spl mu/m CMOS technology. The receiver has a wide dynamic range of more than 25 dB for burst-mode optical input at 29 Mb/s. It has high transimpedance gain of 150 dB/spl Omega/ and high sensitivity of -42 dBm with stable operation for FET threshold voltage and power supply voltage fluctuation. >

A monolithic 156 Mb/s clock and data recovery PLL circuit using the sample-and-hold technique

The PLL circuit described here performs the function of data and clock recovery for random data patterns by using a sample-and-hold technique, and four component circuits (a phase comparator, a delay circuit, a voltage-controlled oscillator, and a S/H switch with a low-pass-filter) were specially designed to further stabilize the PLL operation. A test chip fabricated using Si bipolar process technology demonstrated error-free operation with an input of 2/sup 23/-1 PRBS data at 156 Mb/s. The rms data pattern jitter was reduced to only 1.2 degrees with only an external power supply bypass capacitor. >

Bipolar monolithic amplifiers for a gigabit optical repeater

Main amplifier, AGC amplifier, and preamplifier ICs have been designed and fabricated using an advanced silicon bipolar process to provide the required characteristics of repeater circuits for a gigabit optical fiber transmission system. The bipolar technology used involved a separation width of 0.3 /spl mu/m between the emitter and the base electrode. New circuit techniques were also used. The differential type main amplifier has a peaking function which can be varied widely by means of DC voltage supplied at the outside IC terminal. A bandwidth which can be varied to about three times the value for a nonpeaking amplifier is easily obtained. The gain and maximum 3-dB down bandwidth were 4 dB and 4 GHz, respectively. The main feature of the AGC amplifier is that the diodes are connected to the emitters of the differential transistor pair to improve the linearity. The maximum gain and 3-dB down bandwidth were 15 dB and 1.4 GHz, respectively, and a dynamic range of 25 dB was obtained. The preamplifier has a shunt-series feedback configuration. Furthermore, a gain and 3-dB down bandwidth of 22 dB and 2 GHz, respectively, were achieved with an optimum circuit design. The noise figure obtained was 3.5 dB.

A Design and Packaging Technique for a High-Gain, Gigahertz-Band Single-Chip Amplifier

Equalizing amplifiers for gigabit optical fiber transmission systems requires a 65-dB gain (S21) with a gigahertz bandwidth. However, this gain has the potential to cause significant parasitic oscillation. Consequently, developing a useful stabilization design technique is a very important factor in attaining practical design. In this paper, stabilization design techniques are described for circuit configurations, packaging, and stability assessment. In addition, fabrication results of amplifier IC based on bipolar super self-aligned process technology (SST) and new wide-band high isolation package with coaxial-like 50-/spl Omega/ signal lines are also shown. A 65-dB gain, 1.3-GHz bandwidth single-chip amplifier has been successfully fabricated.

High Gain Equalizing Amplifier Integrated Circuits for a Gigabit Optical Repeater

Equalizing amplifier circuits for a gigabit optical fiber transmission system are integrated on two monolithic chips incrementing an advanced silicon bipolar process. Several new circuit techniques such as a broad band 50 ohm matching amplifier and an electrically controlled and adjusted peaking technique are employed. The gain and maximum 3-dB down bandwidth are 64 dB and 1.2 GHz, respectively. The noise figure obtained is 4.5 dB within the DC to 2 GHz range.

3.3 V, 5O Mb/s CMOS transceiver for optical burst-mode communication

An instantaneous-response CMOS amplifier uses feed-forward. As the LD driver can be realized with CMOS technology more easily than the amplifier, both the AGC amplifier and the LD driver can be integrated in a chip. A 0.8/spl mu/m CMOS process for mass production reduces chip cost. To further reduce cost, it is important to shorten the adjustment time by decreasing the number of circuits requiring adjustment. Conventionally, more than four adjustments are necessary: offset canceling, reference level setting for AGC and comparator and optical output level setting. This problem can be solved by using a CMOS adjustment-free amplifier. The operating margin against process variation is increased by multistage automatic offset canceling (AOC). AOC reduces test time and makes 3.3V operation possible because of the large operation margin.

Circuits to reduce distortion in the diode-bridge track-and-hold

Circuits for reducing distortion in the diode-bridge track-and-hold are described. Adding circuits with current and voltage feedback can reduce distortion caused by the droop and nonlinear junction capacitance of a transistor. A high-speed complementary bipolar process technology is incorporated in the circuit design for its flexibility. SPICE II simulation demonstrates that the circuits reduce distortion in the diode-bridge track-and-hold by 10 to 20 dB. >

An ultracompact, 2-cc-size, 0.64-W 2.5-Gbit/s optical receiver module combined with an MU receptacle

Summary form only given. Recently, optical communication systems have been applied to various field such as local area networks (LANs), optical interconnections, SDH/SONET, and wavelength-division multiplexing (WDM) systems. To achieve these systems cost-effectively, some trials have been made to realize low-power and small-size optical modules. We have developed an ultra-compact and low-power 2.5-Gbit/s optical receiver (OR) module based on a novel structure and advanced IC design. For drastic size reduction, we used the following design schemes: (1) a butterfly package merged with an MU receptacle (MU-R), (2) multichip module (MCM) technology for assembling ICs, and (3) advanced IC design to eliminate external components that obstruct size reduction.