Keith A. Carter

A Fully Integrated MIMO Multi-Band Direct-Conversion CMOS Transceiver for WLAN Applications (802.11n)

A single-chip multi-band direct-conversion CMOS MIMO transceiver (2 times 2) targeted for WLAN applications is presented. This transceiver is capable of satisfying the requirements of the Enhanced Wireless Consortium and achieves PHY rates of >270Mb/s. The receivers and transmitters achieve an EVM of better than -41 dB (0.9%) and -40dB (1.0%) operating in legacy g and a modes, respectively. From a 1.8V supply and with both cores operating, the chip draws 275mA in RX mode and 280mA in TX mode.

A multistandard, multiband SoC with integrated BT, FM, WLAN radios and integrated power amplifier

The growing occurrences of WLAN, BT, and FM on the same mobile device have created a demand for putting all three on the same die to save on die size, I/O count, BOM, and ultimately cost. Common blocks such as crystal oscillator, bandgap, and power management units can be easily shared. This paper presents a solution in which 802.11a/b/g WLAN, single-stream 11n (SSN) WLAN, BT, and FM subsystem and radio are integrated on a single die.

Direct-conversion CMOS transceiver with automatic frequency control for 802.11a wireless LANs

A 11.7mm/sup 2/ 5GHz direct-conversion 0.18/spl mu/m CMOS transceiver achieves a sensitivity of -93dBm, a system NF of 4.5dB (high gain), and IIP3 of -4.8dBm (low gain). Dissipation is 150mW in RX mode and 380mW while transmitting 15dBm OFDM signal.

A Highly Linear Direct-Conversion Transmit Mixer Transconductance Stage with Local Oscillation Feedthrough and I/Q Imbalance Cancellation Scheme

A linear transconductance stage with process insensitive gain control and gain insensitive output offset current is proposed. A calibration scheme to remove the LO feedthrough (LOFT) and I/Q imbalance is also introduced. The prototype achieves 3rd-order IMD suppression better than 52dBc, LOF suppression better than 32dBc, and image rejection better than 46dBc for all gain settings. The transmit chain achieves an 802.11a EVM of < -40dB

A 4.92-5.845 GHz direct-conversion CMOS transceiver for IEEE 802.11a wireless LAN

A fully integrated CMOS direct-conversion 5 GHz transceiver is implemented in a 0.18 /spl mu/m digital CMOS process and housed in an LPCC-48 package. This chip, along with a companion baseband chip, provides a complete 802.11a solution covering all of the world-wide 4.92-5.845 GHz bands. The receiver achieves a 3.5 dB NF while the transmitter achieves a +23 dBm saturated output power. The integrated PA utilizes a linearization technique to allow for high efficiency while maintaining the linear operation required by QAM64 OFDM signals. The transceiver achieves low cost and high yield through the use of various integrated self-contained or system level calibration techniques.

A low insertion loss, high linearity, T/R switch in 65 nm bulk CMOS for WLAN 802.11g applications

A transmit-receiver (T/R) switch is fabricated in a 65 nm CMOS process for WLAN 802.11 g applications. By floating the triple well device, the switch achieves low insertion loss, high power handling capability and good linearity simultaneously. In the transmit mode, the switch features 0.8 dB insertion loss, 29 dBm output P1dB and less than 0.2 dB EVM degradation at 24 dBm output power level. In the receive mode, it exhibits 1.6 dB insertion loss and 28 dB isolation at 2.45 GHz.

A 2×2 MIMO baseband for high-throughput wireless local-area networking (802.11n)

This article consists of a collection of slides from the authors conference presentation on a 2X2 MIMO basedband system for high throughput wireless local area networking. Some of the specific topics discussed include: the demand for wireless LAN, 2000-2011; schemas of multipath channels; exploiting multipath processing for high rates and the impact on energy capacity planning; system architecture for MIMO-ODFM; system processing capabilities and performance summaries; the need for flexible transceivers; and block diagrams and system topologies.