Keith A. Joyner

Shallow trench isolation for advanced ULSI CMOS technologies

This paper reviews the requirements and challenges in designing a Shallow Trench Isolation (STI) process flow for 0.1 /spl mu/m CMOS technologies. Various processing techniques are described for the steps in the STI flow viz. trench definition, corner rounding, gapfill, planarization and well implants. The current capability and scaling requirements for each process step, discussed in the paper, are as follows: (a) Trenches have sidewall angle >/spl sim/80/spl deg/ to maintain trench depth and isolation at narrow space. The trench bottom is rounded to minimize stress. (b) Pad oxide undercut, prior to liner oxidation in halogen ambient or at high temperature, provides adequate corner rounding to suppress edge leakage, with minimum loss of active area. (c) HDP and TEOS-O/sub 3/ CVD oxides can fill 0.16 /spl mu/m wide trenches free of voids. Lower trench aspect ratios (thinner nitride and liner oxide, and shallower trenches), and process improvements allow scaling to smaller dimensions. Gapfill process, liner oxide, and thermal cycles are tailored to prevent stress-induced defects, trench sidewall and corner damage. (d) CMP step height uniformity is improved by using dummy active areas, nitride overlayer or patterned etchback. (e) Optimization of retrograde well and channel stop implants minimizes sensitivity of N/sup +/-P/sup +/ isolation to overlay tolerance and improves latch-up performance.

A shallow trench isolation study for 0.25/0.18 /spl mu/m CMOS technologies and beyond

A manufacturable shallow trench isolation (STI) technology using high density plasma (HDP) CVD oxide as trench filling material is reported for the first time, and compared to using sub-atmospheric CVD (SACVD) oxide as filling material. HDP filled STI has excellent immunity to double-hump, better gate oxide integrity and inverse narrow width effect, due to its lower deglaze rate and thus better corner protection compared to the SACVD case. The /spl Delta/Vt (between W=10 and 0.18 /spl mu/m) are 150 mV (NMOS). And 60 mV (PMOS) for the HDP case, and the transistor width reduction is /spl les/0.03 /spl mu/m for both cases. Trench wall passivation and a low sputtering component during deposition are necessary for HDP to achieve low diode edge leakage. 0.28 /spl mu/m intra-well isolation (or 0.46 /spl mu/m min. pitch), 0.6 /spl mu/m n/sup +/-to-p/sup +/ isolation, latch-up holding voltage of 2 V at 0.5 /spl mu/m n/sup +/-to-p/sup +/ spacing, together with outstanding CMOS transistor and inverter performance, have been achieved. These results are either comparable to or better than the best results reported to date. It is concluded that HDP trench filling oxide is a viable approach, while SACVD oxide is marginally acceptable, for the STI of 0.25/0.18 /spl mu/m CMOS.

A study of floating-body effects on inverter chain delay

Sub and Fossum (1994) predicted that floating-body effects in partially depleted (PD) SOI transistors will cause the performance of a PD/SOI circuit to depend on its recent history. The voltage of the floating body affects the threshold voltage V/sub t/ which results in hysteretic dependence of leakage current and gate delay. The interactions are complex, and experimental data are needed to confirm the model and establish the significance of the effects on circuit performance. The purpose of this work is to advance understanding of hysteretic floating-body effects, the interplay of time constants involved in these processes, and their impact on circuit performance.

ESD design for deep submicron SOI technology [NMOS transistor]

This paper establishes the critical ESD design issues for a partially depleted 0.35 /spl mu/m SOI process. Through device analysis we show for the first time that the gate bias of an NMOS during ESD plays a critical role in reducing channel heating and in achieving good protection levels for both positive and negative stress polarities. With an optimum design window, we demonstrate greater than /spl plusmn/2 kV ESD performance with no additional process steps.

Isolation techniques for 256 Mbit SOI DRAM application

Various isolation techniques on SOI wafer were examined for the 256 Mbit DRAM application. The LOCOS technique results in good isolation down to 0.6 /spl mu/m pitch, in terms of encroachment and subthreshold characteristics. The encroachment of SOI wafers is slightly better than that of bulk wafers on the thick SOI wafers and expect to be even better on the thin SOI wafers. It is the most efficient way to adopt LOCOS isolation for the 256 Mbit SOI DRAM because of many years of process development experience in the bulk technology. In addition, the LOCOS isolation provides no edge leakage to the devices on SOI wafers. However, the LOCOS isolation technique may be limited as the DRAM cell pitch continue to scale down. The MESA isolation provides encroachment free for all ranges of SOI thickness. However, the MESA isolation morphology varies with the size of the isolation region. This could introduce edge leakage in devices with wide isolation region. The morphology variation can be solved with Chemical Mechanical Polishing (CMP) technology and it is expected not to be an issue in the near future. The edge leakage can be suppressed by angled channel stop implant and with mesa corner rounding treatment. As the DRAM cell pitch continue to scale down, the MESA isolation technique may be the only candidate for the 1 Gbit and beyond SOI DRAM.

A closed form analytic model for separation by implantation of oxygen oxide growth using a joined‐Gaussian approximation

A closed form analytic solution to the growth characteristics of the separation by implantation of oxygen (SIMOX) buried oxide and silicon film, based on a two‐sided Gaussian approximation to the oxygen implant profile in the SIMOX process, is presented. The model used includes the effects of substrate swelling and sputtering due to the implanted oxygen, as well as the effects of saturation of the oxygen density at the stoichiometric SiO2 level in the implanted region. The results of this investigation show that for typical SIMOX implant conditions currently used in high‐current implanters, the total dose of oxygen required to first reach the saturation level is only slightly dependent on the swelling and sputtering effects associated with the oxygen implantation, and that the deviation of the location of the first saturation point from the commonly used implant range can be significantly affected by the implant profile. In addition, it is shown that a ‘‘natural parameter’’ GNsat, where G is the net growt...

Direct measurement for SOI and bulk diodes of single-event-upset charge collection from energetic ions and alpha particles

We describe experiments on charge collection from fluorine ions striking ICs and compare with the collection from alpha particles. The fluorine ion strikes are similar to the energetic heavy ions produced when cosmic-ray-generated neutrons collide with silicon nuclei in an IC. The typical measured charge collection is 10 fC for alpha particles and greater than 100 fC for fluorine ions in bulk diodes. For fluorine ions hitting silicon-on-insulator (SOI) diodes, the charge collection is typically less than 9 fC.

Design and performance of SOI pass transistors for 1 Gbit DRAMs

Both partially and fully depleted NMOS pass transistors were designed and fabricated on SIMOX substrates. Using a p+ gate design, V/sub th/=1 V and I/sub off/<1 fA//spl mu/m was achieved on ultra thin film SOI pass transistors. With less than 1 fA//spl mu/m off-state leakage, the SOI pass transistor provides excellent DRAM cell retention time and low stand-by power. The pass transistors junction voltage decay after precharge is much slower on the thin film SOI than on thicker film SOI. In addition, the SOI pass transistors were found to have higher DRAM charging efficiency than the bulk pass transistor due to the elimination of the body effect. The higher charging efficiency of SOI pass transistors allows a reduction in the word line voltage during the charging state, avoiding the need for the usual boosting of the DRAM word line voltage, thereby increasing the gate oxide integrity and decreasing the active power.

Silicon film thickness and material dependence of "reverse short channel effect" for SOI NMOSFETs

Reverse Short Channel Effect (RSCE) effect in SOI devices is observed and is found dependent on silicon overlayer thickness. No correlation between MDD implant dose and RSCE is observed. RSCE is found to depend on material quality. All result can be explained by the dopant (boron) pile-up at the source-drain model.

Effect of particles on buried oxide defects in SIMOX material

An array of artificial particles composed of silicon dioxide was created by growing a film of SiO/sub 2/ one micron thick on a wafer surface, then patterning and etching the film to create barriers of various sizes and shapes. Two of the more interesting of these shapes are long lines and individual dots. These lines make it practical to analyze the structures by cross-sectional scanning and transmission electron microscopy. The shape of one of the lines after implantation to a dose of 1.8*10/sup 18/ at an implantation temperature of 630 degrees C is shown.<<ETX>>