Somnath S. Nag

A shallow trench isolation study for 0.25/0.18 /spl mu/m CMOS technologies and beyond

A manufacturable shallow trench isolation (STI) technology using high density plasma (HDP) CVD oxide as trench filling material is reported for the first time, and compared to using sub-atmospheric CVD (SACVD) oxide as filling material. HDP filled STI has excellent immunity to double-hump, better gate oxide integrity and inverse narrow width effect, due to its lower deglaze rate and thus better corner protection compared to the SACVD case. The /spl Delta/Vt (between W=10 and 0.18 /spl mu/m) are 150 mV (NMOS). And 60 mV (PMOS) for the HDP case, and the transistor width reduction is /spl les/0.03 /spl mu/m for both cases. Trench wall passivation and a low sputtering component during deposition are necessary for HDP to achieve low diode edge leakage. 0.28 /spl mu/m intra-well isolation (or 0.46 /spl mu/m min. pitch), 0.6 /spl mu/m n/sup +/-to-p/sup +/ isolation, latch-up holding voltage of 2 V at 0.5 /spl mu/m n/sup +/-to-p/sup +/ spacing, together with outstanding CMOS transistor and inverter performance, have been achieved. These results are either comparable to or better than the best results reported to date. It is concluded that HDP trench filling oxide is a viable approach, while SACVD oxide is marginally acceptable, for the STI of 0.25/0.18 /spl mu/m CMOS.

Study of integration issues in shallow trench isolation for deep submicron CMOS technologies

This paper presents a study of the issues in integrating the pattern, fill, planarization and surface cleanup processes to design a shallow trench isolation (STI) flow suitable for 0.25 micrometers CMOS technologies. Technological choices and their effects on the characteristics of the STI technology are discussed. Experimental data is presented to illustrate how process choices at various stages of the STI flow are made to optimize the STI structure.