Keith Kwong Hon Wong

Metallization by plating for high-performance multichip modules

Electrolytic plating is used to produce the interconnect wiring on the current generation of high-performance multichip modules used in IBM S/390® and AS/400® servers. This paper reviews the material and manufacturing requirements for successful implementation of a multilayer high-density wiring pattern involving electroplated copper metal and polyimide dielectric. Various strategies for the construction of thin-film structures (planarized and nonplanarized) are outlined, and the advantages of electrolytic plating over dry deposition techniques are described.

Gate length scaling and high drive currents enabled for high performance SOI technology using high-κ/metal gate

CMOS devices with high-k/metal gate stacks have been fabricated using a gate-first process flow and conventional stressors at gate lengths of 25 nm, highlighting the scalability of this approach for high performance SOI CMOS technology. AC drive currents of 1630muA/mum and 1190muA/mum have been demonstrated in 45 nm ground-rules at 1V and 200nA/mum off current for nFETs and pFETs, at a Tinv of 14 and 15 respectively. The drive currents were achieved using a simplified high-k/metal gate integration scheme with embedded SiGe and dual stress liners (DSL) and without utilizing additional stress enhancers. Devices have been fabricated with Tinvs down to 12 and 10.5 demonstrating the scalability of this approach for 32 nm and beyond.

An Analytical Metal Resistance Model and Its Application for Sub-22-nm Metal-Gate CMOS

Gate resistance, middle of line resistance, and back end of line resistance in modern metal-gate CMOS increase drastically as the dimensions of the gates, interconnects and vias scale down close to or below the bulk electron mean free paths (MFPs) of the metal materials. These resistances, especially the gate resistance, impose more and more significant RC delay to CMOS circuits and become significant concerns in sub-22-nm CMOS. In order to optimize the metal-gate materials and structures for low resistance, accurate metal resistance model is needed. In this letter, we propose an analytical metal resistance model applicable for metal wires and films even with sub-MFP sizes. Our model includes scattering effects from surfaces, interfaces, and grain boundaries, and has been successfully verified on W metal gates with the feature sizes ranging from 20 to 70 nm.