Carl J. Radens

Challenges and future directions for the scaling of dynamic random-access memory (DRAM)

Significant challenges face DRAM scaling toward and beyond the 0.10-µm generation. Scaling techniques used in earlier generations for the array-access transistor and the storage capacitor are encountering limitations which necessitate major innovation in electrical operating mode, structure, and processing. Although a variety of options exist for advancing the technology, such as low-voltage operation, vertical MOSFETs, and novel capacitor structures, uncertainties exist about which way to proceed. This paper discusses the interrelationships among the DRAM scaling requirements and their possible solutions. The emphasis is on trench-capacitor DRAM technology.

Fluctuation limits & scaling opportunities for CMOS SRAM cells

Fundamental limitations on scaling CMOS SRAM cell transistor dimensions and operating voltages are demonstrated by measuring the local stochastic distributions of read, write and retention DC margins of 65nm PDSOI CMOS SRAM cells. DC measurements show, for the first time, the write operation to be more fluctuation limited. Measurements also reveal fundamental insights into terminal voltage dependencies of the fluctuations of cell storage node voltages - observations that are engaged to increase cell immunity to fluctuations by several orders of magnitude by biasing the cell terminal voltages appropriately

A Sub-600-mV, Fluctuation Tolerant 65-nm CMOS SRAM Array With Dynamic Cell Biasing

Fluctuation limitations on scaling CMOS SRAM cell transistor dimensions and operating voltages are demonstrated by measuring local stochastic distributions of 65-nm PDSOI CMOS SRAM cell storage node voltages during read, write, and retention modes of operation. These measurements reveal insights into terminal voltage dependencies of cell margin distributions - observations that are engaged to increase cell immunity to random VT fluctuations by several orders of magnitude by biasing the cell terminal voltages dynamically with a read-write asymmetry. Combinations of circuit techniques implementing these dynamic cell biasing schemes are demonstrated in a 9 kb times74 b PDSOI CMOS SRAM array with a conventional 65 nm SRAM cell and an ABIST. Measurements demonstrate these techniques to enable VMIN reductions of over 200 mV - lowering measured VMIN to 0.54 V and 0.38 V/0.50 V for single and dual VDD implementations, respectively. The techniques consume a 10%-12% overhead in area, impact performance marginally (<5%) and also enable over 50% reduction in cell leakage.

A 64 Mb SRAM in 32 nm High-k Metal-Gate SOI Technology With 0.7 V Operation Enabled by Stability, Write-Ability and Read-Ability Enhancements

A 64Mb SRAM macro is fabricated in a 32nm high-k metal-gate (HKMG) SOI technology [1]. Figure 14.1.1 shows the 0.154μm2 bitcell (BC). A 2× size reduction from the previous 45nm design [2] is enabled by an equal 2× reduction in BC area. No corner rounding of BC gates allows tighter overlay of gate electrode and active area. The introduction of HKMG provides a significant reduction in the equivalent oxide thickness, thereby reducing the Vt mismatch. This reduction allows aggressive scaling of device dimensions needed to achieve the small area footprint. A 0.7V VDDMIN operation is enabled by three assist features. Stability is improved by a bitline (BL) regulation scheme. Enhancements to the write path include an increase of 40% of BL boost voltage. Finally, a BC-tracking delay circuit improves both performance and yield across the process space.

Plasma immersion ion implantation as an alternative deep trench buried-plate doping technology

Plasma immersion ion implantation (PIII) has been developed as an alternative deep trench capacitor buried-plate doping technology and compared to a conventional solid-state diffusion technique using arsenosilicate glass (ASG). Novel top-down (or vertical) SIMS measurements demonstrated the conformal doping capability of PIII along the trench sidewall. The doping level by PIII was almost one order of magnitude higher than that by a conventional technique. As a consequence, PIII provided better depletion characteristics than conventional technique. Furthermore, PIII processing did not degrade node-to-buried plate leakage current characteristics. From these results, it was demonstrated that PIII is a promising technology as an alternative deep trench capacitor buried-plate doping technique for future deep trench-based DRAM processing development.

Thickness and polarity dependence of intrinsic breakdown of ultra-thin reoxidized-nitride for DRAM technology applications

This paper discusses the charge-trapping and intrinsic breakdown characteristics of ultra-thin reoxidized nitride with deep-trench capacitor structures for a range of thickness, voltages, and temperatures. Strong polarity dependence of charge-trapping and time-dependent dielectric breakdown (TDDB) is reported. For the first time, a physical model is proposed to relate the asymmetric charge injection and trapping to this intrinsic breakdown characteristic in thin reoxidized nitride. The thickness dependence of TDDB is also investigated and used for a reliability projection of the oxide equivalent thickness down to 2.9 nm.

Super Fast Physics-Based Methodology for Accurate Memory Yield Prediction

We propose an efficient physics-based mixed-mode statistical simulation methodology for nanoscale devices and circuits. Here, 3-D Technology Computer Aided Design models pose a barrier for efficient simulation of variability as they generally involve millions of nodes in their mesh representations. The proposed methodology, which has been implemented for FinFET/tri-gate static random access memory (SRAM) design, overcomes this barrier by leveraging advanced physics-based 2-D (P2-D) devices with optimized meshes that are derived from 3-D FinFET models with tuned device parasitics. This enables physics-based simulation as well as physics-based variability input parameters. To improve accuracy, an embedded automated flow enables extraction of all external nodal parasitics, directly from a 3-D FinFET circuit layout representation. The circuits consisting of advanced P2-D devices are then back annotated with the nodal parasitics to enable fast and accurate SRAM dynamic margin mixed-mode simulations. Results demonstrate up to 200× speedup compared with traditional 3-D device simulations, and around five orders of magnitude wall clock time improvement on account of fast statistical methodologies, which are superior in comparison with traditional Monte Carlo analysis. This makes it feasible to supplant often inaccurate compact model-based simulations by true mixed-mode device simulations in statistical engines. The proposed physics-based methodology is also shown to corroborate well with hardware measurements.

Technologies for scaling vertical transistor DRAM cells to 70 nm

Vertical transistor DRAM cells have been demonstrated as viable in the 110 nm generation. This paper describes the issues associated with scaling these cells to the 70 nm node and demonstrates fixes to all known issues. Scaling to 70 nm is possible through the development of two key enabling technologies, high aspect ratio STI fill and low resistance metal deep trench fill, and through minor cell modification. Each of these items are addressed and shown to be viable using a functional 512 Mb prototype DRAM chip at 110 nm half-pitch groundrule. Based on these results, we believe the vertical transistor DRAM cell is one of the most promising for continued scaling of conventional DRAM and embedded DRAM cells.

1.5-V single work-function W/WN/n/sup +/-poly gate CMOS device design with 110-nm buried-channel PMOS for 90-nm vertical-cell DRAM

This letter reports on 1.5-V single work-function W/WN/n/sup +/-poly gate CMOS transistors for high-performance stand-alone dynamic random access memory (DRAM) and low-cost low-leakage embedded DRAM applications. At V/sub dd/ Of 1.5-V and 25/spl deg/C, drive currents of 634 /spl mu/A//spl mu/m for 90-nm L/sub gate/ NMOS and 208 /spl mu/A-/spl mu/m for 110-nm L/sub gate/ buried-channel PMOS are achieved at 25 pA//spl mu/m off-state leakage. Device performance of this single work function technology is comparable to published low leakage 1.5-V dual work-function technologies and 25% better than previously reported 1.8-V single work-function technology. Data illustrating hot-carrier immunity of these devices under high electric fields is also presented. Scalability of single work-function CMOS device design for the 90-nm DRAM generation is demonstrated.

An orthogonal 6F/sup 2/ trench-sidewall vertical device cell for 4 Gb/16 Gb DRAM

This paper describes a novel 6F/sup 2/ trench-capacitor DRAM with a trench-sidewall vertical-channel array transistor. The cell features a line/space pattern for the active area, single-sided buried-strap node contact, vertical transistor channel formed along the upper region of the trench capacitor, a device active area bounded by the isolation trench and capacitor collar, and a single bit contact per cell.