Kelly J. Taylor

Thermomechanical properties and moisture uptake characteristics of hydrogen silsesquioxane submicron films

This letter describes measurement of the biaxial modulus, coefficient of thermal expansion (CTE), and moisture uptake characteristics of hydrogen silsesquioxane (HSQ) thin films. The biaxial modulus and CTE were determined using a bending beam method, and moisture uptake was studied using a quartz crystal microbalance method. The biaxial modulus and CTE of a 0.5 μm HSQ film were measured on Si and Ge substrates and found to be 7.07 GPa and 20.5 ppm/°C, respectively. The value determined for the diffusion constant of water in a 0.7-μm-thick HSQ films is 3.61×10−10 cm2/s at room temperature.

Highly porous interlayer dielectric for interconnect capacitance reduction

Hydrogen silsesquioxane (HSQ) is a low density material for intra-metal gapfill, that offers low permittivity for interconnect capacitance reduction. Films with k as low as /spl sim/2.2 preferentially form between tightly-spaced metal leads when cured at low temperature (<400/spl deg/C), and interlayer dielectric properties are stable from 1 MHz to 1 GHz. HSQ simplifies the process integration of low-k materials for high performance interconnect applications by using standard semiconductor spin-on production techniques. Use of porous HSQ as a gapfill dielectric dramatically reduces the capacitive coupling between metal leads, resulting in higher interconnect performance.

Deposition and Characterization of Porous Silica Xerogel Films

The continued scaling of device feature size demands the use of low permittivity intermetal dielectric materials. Porous silica xerogel films have low dielectric permittivity through the incorporation of micropores into the SiO 2 network. A feasible xerogel process has been developed. Crack-free and uniform silica xerogel films up to two microns in thickness with targeted porosity were readily coated. Xerogel materials completely filled 0.3 μm wide gaps with a 2:1 aspect ratio. MOSCAP measurements revealed a low permittivity and high dielectric breakdown strength. The dielectric breakdown strength is expected to be higher than that of ambient air because the average pore size of in the xerogel film is much smaller than the mean free path of the ambient air. Surface treated xerogel films were found to be hydrophobic as indicated by the absence of adsorbed moisture peaks in FTIR spectra. Xerogel films maintained their porosity after deposition of dense capping layers and a subsequent process under 700 atm Ar pressure at 400 °C. Test structures containing xerogel were successfully planarization with CMP and went through a tungsten plug deposition process without delamination nor collapsing. These results reflect the reasonable mechanical strength of xerogel films.

Process Integration Of Low-Dielectric-Constant Materials

As device geometries and operating voltage continue to scale while functional density increases, it is imperative to reduce the RC time delay. The replacement of Si0 2 as an intermetal dielectric with an insulator of lower dielectric constant is a particularly attractive solution since it provides immediate performance improvement through reduction in capacitance. An embedded polymer integration scheme improves the interconnect performance through line-to-line capacitance reduction by using polymer only between tightly spaced lines. The gapfill polymeric materials do not degrade the electromigration performance of standard multilayered TiN/Al/TiN interconnects. Embedded polymers alleviate many of the integration and reliability problems associated with polymer integration, and can be easily adopted into a standard production process.

Chemical mechanical planarization of multilayer dielectric stacks

Sub-0.5 micrometers multilevel metal schemes impose stringent requirements on both gap-fill and planarity of interlevel dielectrics. A variety of novel materials and processes are being investigated to meet these process requirements. In this paper, four dielectrics with good gap- filling capabilities are evaluated for planarity characteristics: SiO2 deposited using a high density plasma (HDP) with simultaneous deposition and sputtering, an organic spin-on-glass material SOG-A, an inorganic spin-on-glass material SOG-B, and SiO2 deposited using ozone and TEOS at sub-atmospheric pressure (SACVD). These materials are used for gap-fill followed by a capping layer of PETEOS. For global planarization, only the top layer of PETEOS is planarized using chemical mechanical polishing (CMP) without exposing the underlying gap-fill material. Planarization characteristics of the dielectric stacks are found to be significantly different, both before and after CMP. The CMP throughput is found to be very sensitive to the choice of the dielectric stack. For a given planarity goal, the CMP throughputs of three of the dielectric stacks are found to be significantly higher than that of a conventional single layer interlevel dielectric (ILD) consisting of only PETEOS.

An integrated low resistance aluminum plug and low-k polymer dielectric for high performance 0.25 /spl mu/m interconnects

Low temperature aluminum plug fill schemes such as CVD Al and high pressure ForceFill/sup TM/ Al offer significant advantages in terms of lower via resistance and compatibility with low-k polymer dielectrics. The low processing temperature is desirable for advanced high performance sub-half micron interconnects with polymeric dielectrics. While the CVD Al process enables sub-300/spl deg/C plug processing, the ForceFill/sup TM/ process has also been shown to of relatively low temperature (400/spl deg/C). An embedded dielectric scheme is particularly attractive for integrating polymeric materials as this structure offers improved structural stability and alleviates many of the difficulties associated with via process integration. In this paper we present a comparison of CVD Al and ForceFill/sup TM/ Al for double level metal structures using embedded low-k dielectrics such as Parylene (N) (k=2.7) and Hydrogen Silsesquioxane (HSQ). Integration of Al and Parylene is shown to provide significant performance advantage for metal RC delay.

Antenna damage from a plasma TEOS deposition reactor: Relationship with surface charge and RF sensor measurements

We identified antenna damage associated with a PECVD (plasma enhanced chemical vapor deposition) TEOS (tetraethoxysilane) process for interlevel dielectric deposition. The damage was isolated to the terminating steps in the recipe depositing 1000 /spl Aring/ of SiO/sub 2/. V/sub s/ (surface charge) measurements on the Keithley Quantox along with our CMOS test chip were used for further characterization of the terminating steps. At the same time, an RF sensor was used to identify the plasma characteristics of the chamber. A design of experiments was done around the RF power and chuck-to-wafer spacing in the terminating sequence in order to minimize damage to the antenna.

Simultaneous control of multiple measures of nonuniformity using site models and monitor wafer control

Present day semiconductor manufacturing processes are subject to tight specifications. High yields with tight process specifications require drive to target process control. As the size of the wafer in the semiconductor industry increases, nonuniformity across the wafer becomes a crucial yield limiting issue. Modeling nonuniformity in terms of the equipment settings permits calculation of recipes required to achieve the desired nonuniformity. However, models for single measures of nonuniformity, such as standard deviation, or range, do not capture all aspects of the nonuniformity and often do not model well in terms of the equipment settings. This paper describes the use of spatial models to simultaneously quantify multiple measures of nonuniformity, and a controller to keep the nonuniformities within specifications, Use of spatial models in conjunction with a monitor wafer controller (MWC) enables the simultaneous control of multiple nonuniformity measures. The paper presents the results of applying the MWC with spatial models to a plasma enhanced TEOS (PETEOS) deposition process on an Applied Materials Precision 5000 (AMT5000). The controller has been keeping the PETEOS process within specifications for over two years.

Polymers for high performance interconnects

It is well-known that capacitance in the metallization is becoming too great to allow the continued use of SiO/sub 2/ as the intermetal dielectric below about the 0.25 /spl mu/m technology node. One of many possible replacements for SiO/sub 2/ are organic polymers. Organic polymers are not drop-in replacements, however, and their successful integration into functional circuits requires new fabrication procedures and integration schemes. The embedded dielectric scheme offers a sound evolutionally path for their successful integration into a subtractive etch, aluminum-based integrated circuit. The embedded dielectric scheme effectively lowers total capacitance and the line-line/total capacitance ratio while minimally changing the rest of the metallization fabrication processes including via formation. Vapor deposited polymers which are conformably deposited like Parylene-n are more easily integrated into the embedded dielectric scheme than nonconformal spin-on dielectric films. Parylene-n copolymers with dielectric permittivities as low as 2.3 also are excellent candidate materials for use in the embedded dielectric scheme and they also have equivalent thermal stability as the homopolymer. New copolymers with comonomers of different functionality should improve both the adhesion and thermal stability of the intermetal dielectric.

Nondestructive, at-line measurement of dielectric constant for VLSI intermetal dielectrics

Shrinking VLSI metallization schemes require new intermetal dielectrics (IMD) with low dielectric constant, K. Materials being considered are doped glasses, polymers, porous material and composites. Both the magnitude and the variability of the dielectric constant must be measured for these new dielectrics, hence, a new need to make reliable, accurate and cost-effective at-line measurements of the dielectric constant has emerged. We have developed a technique using commercially available, non contact capacitive probe and spectral ellipsometry tools to measure K to an accuracy of better than 5% at K<4.0. The accuracy and measurement system error improves as K decreases, so that measurements at K=2.0 should be accurate to 2%.