Asad M. Haider

MIM capacitors and methods for fabricating same

Process and integration scheme for a high sidewall coverage ultra-thin metal seed layer

DOUBLE WAFER CARRIER PROCESS FOR CREATING INTEGRATED CIRCUIT DIE WITH THROUGH-SILICON VIAS AND MICRO-ELECTRO-MECHANICAL SYSTEMS PROTECTED BY A HERMETIC CAVITY CREATED AT THE WAFER LEVEL

System and method to form improved seed layer

Silicon nitride/oxygen doped silicon carbide etch stop bi-layer for improved interconnect reliability

Ultra-clean wafer chuck assembly for moisture-sensitive processes conducted in rapid thermal processors

Integrated circuit structure with capacitor and resistor and method for forming

Semiconductive device fabricated using subliming materials to form interlevel dielectrics

INTEGRATED CIRCUIT WITH MICRO INDUCTOR AND MICRO TRANSFORMER WITH MAGNETIC CORE

Novel barrier integration scheme for high-reliability vias