Ken Shono

SEILA: Soft error immune latch for mitigating multi-node-SEU and local-clock-SET

We have developed a robust latch for achieving high reliability in LSI. The latch can attenuate multi-node single-event-upset (MNSEU) and single event transient on local-clock (SETLC). The robust latch has Dual-clock-buffers (DCB) and Double-height-cell (DHC) technologies. Results on neutron acceleration experiments show that DHC can dramatically attenuate MNSEU and DCB can protect almost SETLC of the latch. In addition, we investigate optimum design in well structure.

Stress migration phenomenon in narrow copper interconnects

Stress migration (SM) behavior in Cu damascene interconnects was investigated in detail using different kinds of test patterns. SM failure was found in narrow lines that are very long, or connecting to a wide line. In the pattern in which narrow lines are connected to wide metal, the failure rate decreased as the narrow metal becomes longer. It was found that the failure rate in minimum 0.14μm wide lines is more than that in 0.2–0.42μm wide lines. The result of the test patterns with different via arrangements clarified that the placing of the vias at the edge of the M1 line plays an important role in the SM phenomenon in narrow copper lines. Failure analysis using scanning transmission electron microscopy revealed voiding beneath the via at the failure points for all test patterns. It is shown that the enhanced failure rate in the minimum wide lines and the via arrangement effect cannot be understood by the previous diffusion mechanism. Based on these results, the effect of the via arrangement close to t...

600 V JEDEC-qualified highly reliable GaN HEMTs on Si substrates

In this paper, we demonstrate 600 V highly reliable GaN high electron mobility transistors (HEMTs) on Si substrates. GaN on Si technologies are most important for the mass-production at the Si-LSI manufacturing facility. High breakdown voltage over 1500 V was confirmed with stable dynamic on-resistance (RON) using cascode configuration package. These GaN HEMT on Si based cascode packages have passed the qualification based on the standards of the Joint Electron Devices Engineering Council (JEDEC) (1-5) for the first time. High voltage acceleration test was performed up to 1150 V. Even considering most conservative failure mechanism, mean time to failure (MTTF) of over 1×107 hours at 600 V was predicted at 80°C. Additional conclusion is that conventional packages such as TO-220 are still suitable for high speed circuit application without using a specific gate driver. Ultimately GaN will significantly reduce conversion losses endemic in all areas of electricity conversion, ranging from power supplies to PV inverters to motion control to electric vehicles, enabling consumers, utilities and governments to contribute towards a more energy efficient world.

Commercialization and reliability of 600 V GaN power switches

The reliability of 600 V GaN power switches, fabricated in a silicon CMOS foundry, has been demonstrated. JEDEC qualification of cascode packages and the long term reliability of GaN power switches has been estimated for the first and shown to be greater than a million hours. Excellent switched/dynamic on-resistance up to 1000 V and breakdown voltage over 1500 V indicate the suitability of these devices for switching up to 480 V. Detailed data of high temperature reverse bias (HTRB) test is shown. High temperature DC stress test and high voltage off-state stress tests also corroborate the high reliability of these devices. This suite of initial, JEDEC & accelerated stress tests show that GaN-on-silicon power switches are ready for many commercial and industrial applications, would significantly reduce switching losses and system size and will impact all areas of electricity conversion, ranging from tablet chargers to photovoltaic inverters and electric vehicles.

Investigation of stress-induced voiding inside and under VIAS in copper interconnects with “wing” pattern

Stress induce voiding (SIV) inside and under vias in copper interconnects with ldquowingrdquo-pattern were investigated for 90 nm and 65 nm node processes. The difference of two voidings are the resistance change during acceleration test and the diffusion path. However, common features were found between both types of voiding; the interconnect fails fast as the ldquowingrdquo area grows. Both types of voiding have a critical ldquowingrdquo area where failure never occurs. Both of voiding is more affected by diffusion source than by stress gradient.

Mechanism of AC electromigration

A model for the mechanism of AC electromigration based on the thermal response of Al stripes is proposed. The model is based on the temperature difference between the positive period and the negative period. The thermal time constant of the Al stripe, underlying SiO/sub 2/, and Si substrate is on the order of microseconds and that of the package and ambient is a few seconds. When the cycle time of the current is longer than thermal time constant, the temperature of the Al stripes obeys the current waveform. When the cycle time is shorter than the thermal time constant, the temperature keeps constant. Mean time to failure (MTF) depends on the temperature according to Arrheniuss equation. The temperature difference between positive and negative periods causes an unbalance of atomic flux between the periods. Thus, open-circuit failure can take place under AC conditions.<<ETX>>

Study of Stress Migration Failure in SiLK™/SiO2 Hybrid Cu Interconnects

Stress migration (SM) behavior is studied for a 130nm‐node SiLK™/SiO2 hybrid structure in which the interlevel dielectrics (ILD) consist of SiLK™ for trench levels and SiO2 for via levels. The failure rate dependence on the temperature, line width and circuit is examined in detail. Furthermore, an effect of dielectric deposition process on the reliability of the hybrid interconnects is investigated. It has been found that SM behavior is essentially similar to that reported in Cu/SiO2 systems. It has also been clarified that SiO2 PVD conditions at via level had a large impact on the failure rate. Therefore, the control of ILD deposition conditions is found to be one of the key factors in suppressing the SM failure. In order to examine the effect of the PVD conditions, the residual stress in vias were measured by using X‐ray diffraction method. The results show that σx (the stress component parallel to the surface) in vias greatly depends on the PVD conditions. Then, the relationship between the PVD conditi...