H. Ehara

Measurement and analysis of neutron-induced soft errors in sub-half-micron CMOS circuits

Neutron-induced soft error rates (SERs) of subhalf-micron CMOS SRAM and Latch circuits were studied both experimentally and analytically to investigate cosmic ray neutron-induced soft errors (SEs). Because the neutron beam used in the measurement has an energy spectrum similar to that of sea-level atmospheric neutrons, our SER data corresponds to those induced by cosmic ray neutrons. The /spl alpha/-particle induced SERs were also measured for comparison with the neutron-induced SERs. Neutron-induced SEs occurred in both circuits. On the other hand, /spl alpha/-induced SEs occurred in SRAM, but not in the Latch circuits. The measured SERs agreed with simulated results. We discussed the significance of how cosmic ray neutrons affects CMOS circuits at ground level.

Impact of cosmic ray neutron induced soft errors on advanced submicron CMOS circuits

We numerically studied the neutron effects on submicron CMOS SRAM and LATCH circuits using a developed simulator which agrees well with the experimental charge collection measurements. We showed that the neutron effects have influence on SEs in advanced integrated circuits, especially for LATCH. If the Pb-Sn solder or other materials with high /spl alpha/-particle emission rates are not included, the neutrons are main SE components in advanced integrated circuits.

Cosmic ray neutron-induced soft errors in sub-half micron CMOS circuits

We numerically investigated cosmic ray neutron-induced soft errors in sub-half micron CMOS SRAM and latch circuits at sea level. For our purpose, we developed an original simulator which reproduces well the experimental charge collection data. We investigated soft error rates (SERs) and showed that the neutron-induced SERs in the SRAM are the same order as those due to /spl alpha/-particles and the SERs in the latch are dominated by neutrons.

Measurements and analysis of neutron-reaction-induced charges in a silicon surface region

We directly measured neutron-reaction-induced charges in the silicon surface region using silicon-on-insulator (SOI) test structures. Because the neutron beam used has an energy spectrum similar to that of sea-level atmospheric neutrons, our charge collection data correspond to those induced by cosmic ray neutrons. Measured charge collection spectra were dependent on the SOI thickness and agreed with simulated results. An application for the neutron-induced upset rate prediction was also discussed. Furthermore, the charge collection components were separated by our charge collection simulator.

Simultaneous measurement of soft error rate of 90 nm CMOS SRAM and cosmic ray neutron spectra at the summit of Mauna Kea

We carried out simultaneous measurement of SERs and cosmic ray neutron spectra for the first time. We measured SERs using 90 nm CMOS SRAM chips and measured neutron spectra using a Bonner multisphere spectrometer. We carried out the SER field measurement at the 4200 m summit of Mauna Kea, which is the most suitable place for SER field measurements because the neutron flux is over 10 times greater there than that at sea level. Therefore, we could avoid making field measurements that usually require a long measuring time (about a year) to obtain sufficient accuracy.

Investigation of stress-induced voiding inside and under VIAS in copper interconnects with “wing” pattern

Stress induce voiding (SIV) inside and under vias in copper interconnects with ldquowingrdquo-pattern were investigated for 90 nm and 65 nm node processes. The difference of two voidings are the resistance change during acceleration test and the diffusion path. However, common features were found between both types of voiding; the interconnect fails fast as the ldquowingrdquo area grows. Both types of voiding have a critical ldquowingrdquo area where failure never occurs. Both of voiding is more affected by diffusion source than by stress gradient.

1st quantitative failure-rate calculation for the actual large-scale SRAM using ultra-thin gate-dielectric with measured probability of the gate-current fluctuation and simulated circuit failure-rate

We investigated the influence over intermittent SRAM failure by gate current, Ig, fluctuation for the first time. In this paper, we also describe the difference of SRAM failure due to Ig fluctuations between MOS transistors before and after stressing. We have quantitatively confirmed that Ig fluctuation causes SRAM failure.

Re-think stress migration phenomenon with stress measurement in 12 years

We measured Internal residual stress change in the copper interconnect in 12 years to confirm the phenomenon that is occurred in acceleration test are equivalent with that is occurred in use condition or not. We have compared the stress change results and void feature and acceleration test results. With these results, we think same phenomenon (void generate on the surface of the interconnect) occur in the room temperature long time storage with high temperature storage. Also, we reviewed the FEM result of residual stress. There are not so large stress at the surface of the line. However void occurs on the surface especially for the Wide Pattern. That suggests diffusion path plays important role in accelerated and use condition.

Voiding generation in copper interconnect under room temperature storage in 12 years

We measured the internal residual stress change of ULSI copper interconnects at room temperature for 12 years to confirm the stress migration phenomenon. The residual stress decreased and voids were generated. Furthermore, we investigated the stress change results and void features obtained through physical analyses. The voids had the same features as those in the high-temperature storage. The estimated volume shrinkage agreed with the total volume of the observed voids, suggesting that void generation causes the decrease in stress. From the obtained result, we conclude that the stress migration degradation phenomenon occurs even at room temperature in the long-term storage, and that the void feature is almost identical to that in the high-temperature acceleration test.

Technology Trend of Soft Errors based on Accurate Estimation Method

Y. Tosaka, R. Takasu, H. Ehara*, T. Uemura, H. Oka, S. Satoh, N. Matsuoka**, and K. Hatanaka** Fujitsu Laboratories Ltd., 50 Fuchigami, Akiruno, Tokyo 197-0833, Japan. Phone: +81-42-532-1438, Fax: +81-42-532-2908, E-mail: tosaka@flab.fujitsu.co.jp *Fujitsu Ltd., 50 Fuchigami, Akiruno, Tokyo 197-0833, Japan. **Reserch Center for Nuclear Physics, Osaka University, 10-1 Mihogaoka, Ibaraki, Osaka 567-0047, Japan.