Ken Tanabe

Power-amplifier module with digital adaptive predistortion for cellular phones

This paper describes a new type of PA-module which contains a predistortion function and the application to N-CDMA handset terminals. The predistortion technology is based on look-up-table method using the input and output signal envelopes and can operate independent from the base-band block. By omitting the adaptative predistortion for AM/PM, and integrating main controlling functions on CMOS IC chip, the predistortion technique has been realized in a PA-module. The PA-module has been achieved the power added efficiency (PAE) of 48% at the output power of 27.5 dBm. This PAE is extremely high in comparison with the conventional PA-module for N-CDMA.

A 1.0 V 40mW 10b 100MS/s pipeline ADC in 90nm CMOS

A 1.0V 10b 100MS/s pipeline ADC consuming 40mW fabricated in a 90nm CMOS process is described. Design consideration for the thermal noise of operational amplifiers effectively saves the power consumption of the ADC with conventional architecture at 1.0 V supply. Measured peak SNDR of the ADC is 56.5dB. It occupies 0.52 mm2 with on-chip decoupling capacitors and 0.31 mm2 without the capacitors, both of which includes the buffer for reference voltages

A 6-bit arbitrary digital noise emulator in 65nm CMOS technology

An arbitrary noise generator (ANG) is based on time-series charging of divided parasitic capacitance (TSDPC) and emulates power supply noise generation in a CMOS digital circuit. A prototype ANG incorporates an array of 32 × 32 6-bit TSDPC cells along with a 128-word vector memory and occupies 2 × 2 mm2 in a 65 nm 1.2 V CMOS technology. Digital noise emulation of functional logic cores such as register arrays and processing elements is demonstrated with chip-level waveform monitoring at power supply, ground, as well as substrate nodes.