Hirotomo Ishii

A 1.0 V 40mW 10b 100MS/s pipeline ADC in 90nm CMOS

A 1.0V 10b 100MS/s pipeline ADC consuming 40mW fabricated in a 90nm CMOS process is described. Design consideration for the thermal noise of operational amplifiers effectively saves the power consumption of the ADC with conventional architecture at 1.0 V supply. Measured peak SNDR of the ADC is 56.5dB. It occupies 0.52 mm2 with on-chip decoupling capacitors and 0.31 mm2 without the capacitors, both of which includes the buffer for reference voltages

28.7 A 0.7V 12b 160MS/s 12.8fJ/conv-step pipelined-SAR ADC in 28nm CMOS with digital amplifier technique

Wireless standards, e.g. 802.11ac Wave 2 and 802.11ax draft, aim to boost user throughput to cope with growing data traffic. High-speed (fs>100MS/s) and high-resolution (ENOB>9.5b) ADCs are essential for leading-edge wireless SoCs, given the bandwidth and PAPR specifications. Also, low power dissipation (FoM<20fJ/conv) is crucial for mobile applications. A number of pipelined-SAR ADCs have been presented which satisfy these design targets [1–3]. However, in deep submicron CMOS, design of a high DC-gain opamp for the MDAC is a serious obstacle due to reduced intrinsic transistor gain and sub-1V supply voltage. Hence, all designs utilize digital calibration to counter gain error and tolerate the use of a low-gain amplifier. Calibration times of at least several tens of ms are required, resulting in lengthy start-up times and reduced SoC power efficiency. Moreover, such calibration cannot track sudden supply voltage variations and suppressing such fluctuations with bypass capacitors significantly impacts chip cost [1–2]. Furthermore, amplifier non-linearity remains unsolved; with lower supply voltages, the limited amplifier swing tightens SAR noise requirements.

A power-scalable zero-crossing-based amplifier using inverter-based zero-crossing detector with CMFB

A zero-crossing based amplifier whose power is scalable to a sampling frequency is presented. An inverter-based zero-crossing detector (ZCD) is proposed to consume no static power consumption compared with a conventional ZCD using a class-A based preamplifier. A common-mode feedback (CMFB) circuit is adopted to calibrate a variation of a ZCD threshold voltage due to supply voltage and temperature (VT) variations. In addition, the CMFB enables an only single transfer phase for high speed operation. An 11-bit pipelined successive approximation register (SAR) ADC was designed in a 65-nm CMOS technology and a total active area is 0.15 mm2. The post-layout transient noise simulation result shows the signal-to-noise-and-distortion ratio (SNDR) is 60.6 dB at 100 MS/s from a 1.2 V supply voltage. The proposed amplifier consumes 746 uA at 100 MS/s, 376 uA at 50 MS/s and 208 uA at 25 MS/s, respectively.

Issues of Mixed-Signal Circuit Design in 90nm CMOS LSI Technology

Whereas digital parts of a SoC become smaller every year with device shrink, the shrink doesn’t go ahead in the analog parts because of limitation of operation voltage, therefore the area ratio of analog parts in a SoC becomes bigger year by year (Fig. 1 (a)). Also, high-speed signal processing is accelerated with device shrink of digital parts and it becomes indispensable to integrate a high speed serial interface on a SoC (Fig. 1 (b)). Furthermore, because higher data rate reading is speeded up in a read channel of HD / DVD, power lowing of high speed A/D converter is necessary. Therefore, even in an analog circuit, downsizing, high speed and low power are strongly required in recent years. On the other hand, there are many issues to consider for device shrink and low voltage operation of an analog circuit and the issues will be discussed in this paper taking 90nm CMOS as an example.