Kenichi Matsushita

Critical IGBT Design Regarding EMI and Switching Losses

Critical N-base layer design in IGBT is discussed regarding electro-magnetic interference (EMI) and switching losses during turn-off. The newly proposed criteria for oscillation and avalanche induced loss were given by a simple equation model and the validity of the model has been confirmed with experimental results. This paper shows an efficient design method of N-base for EMI-free IGBT with considering the turn-off loss. In addition, EMI reduction structure with partly buried N layer in N-base was proposed for break through the design limit of N-base.

ESD protection structure with novel trigger technique for LDMOS based on BiCD process

This paper presents ESD protection structure with novel trigger technique for LDMOS based on BiCD process. The proposed ESD protection element includes the same structure as drain region in Nch-LDMOS, the vertical NPN transistor and the lateral NPN transistor. The trigger voltage is depended on the breakdown voltage in the drain region integrated in ESD protection device and the avalanche current acts as the base current of NPN transistor. The high ESD current spreads to the buried layer in the vertical NPN transistor without locally concentrating in the drain edge. The value of the second breakdown trigger current It2 in the proposed ESD protection element is nearly four times as large as that in the simple LDMOS.

Optimization of 5V power devices based on CMOS for hot-carrier degradation

We propose “power CMOS,” suitable for use as large current output devices. The proposed structure can be fabricated by low cost 0.6um logic CMOS process and assures long-term reliability even under the stress of hot-electrons. The developed power CMOS have achieved low specific on resistances of 8.1m: mm 2 for NMOS and 21.1m: mm 2 for PMOS.

Low gate capacitance IEGT with Trench Shield Emitter (IEGT-TSE) realizing high frequency operation

A novel IEGT (Injection Enhanced Gate Transistor) design for drastically reducing of gate capacitance has been proposed in this work. The device structure named IEGT-TSE (IEGT with Trench Shield Emitter) has a dummy trench electrode connected to an emitter electrode. It shields gate electrode from floating p-well during switching. To demonstrate this effect, we exhibit switching waveforms by a numerical simulation and a fabricated device at 1200 blocking voltage class.

High-Voltage Emitter Short Diode (ESD)

We report the effects of emitter short structures, ESD(a) and ESD(b), as well as the effect of a very shallow emitter, on the reverse recovery characteristics for 4 kV high-voltage diodes. It was found that a diode with a shallow p-emitter and emitter short structures attains half the reverse recovery current I rr, compared to conventional punch-through p-i-n diodes. ESD has a further advantage in that the leakage current is as low as that of conventional p-n junction diodes, even at 125° C. ESD structures with a fine n+ and p+ short structure attain no parasitic effect, even at a current density of 100 A/cm2 and di/ dt of -1000 A/µs.