Norio Yasuhara

Breakdown voltage enhancement for devices on thin silicon layer/silicon dioxide film

Studies of high-voltage lateral device structures on a thin silicon layer over silicon dioxide have been carried out. It was found both theoretically and experimentally that over 600-V devices can be realized using a structure consisting of an n diffusion layer over a 15- mu m-thick high-resistivity n/sup -/ silicon layer over 3- mu m silicon dioxide (SOI). A method is presented to enhance breakdown voltage by applying a large share of the voltage to the bottom oxide. >

Low gate charge 30 V n-channel LDMOS for DC-DC converters

We have developed low on-resistance and low feedback gate charge 30 V n-channel LDMOS for MHz switching DC-DC converter applications. The feature of the device is that it has achieved a high avalanche capability of more than 20 amperes together with Ron/spl dot/Qqd value of 10 m/spl Omega/nC, which is the lowest, ever reported for 30 V devices. A low gate resistance of 0.4 /spl Omega/ was achieved by two layer metal electrodes. These features are desirable for MHz switching frequency DC-DC converters to obtain higher efficiency. Good avalanche capability of 20 amperes is achieved under unclamped inductive switching (UIS) condition.

Multi-channel SOI lateral IGBTs with large SOA

We report, for the first time, the development of 5 ampere multi-channel lateral IGBTs on SOI. The new LIGBTs are characterized by a plural number of parallel stripe poly-silicon gates and resultant plural number of channels, which enhances electron injection and attains a large current capability. The developed LIGBTs conduct current density over 120 A/cm/sup 2/ at the drain voltage of 3 V and simultaneously achieve a fall-time below 300 ns. The LIGBTs have excellent current capability and short circuit withstanding capability of DC 300 V with 500 A/cm/sup 2/ of drain current even at 200/spl deg/C.

Numerical analysis of SOI IGBT switching characteristics-switching speed enhancement by reducing the SOI thickness

The electrical characteristics of SOI (silicon-on-insulator) IGBTs (insulated-gate bipolar transistors), including breakdown voltage are discussed. It is found that the switching speed of an IGBT on a thin SOI is improved by reducing the SOI layer thickness without special design optimization. Carrier recombination at the Si-SiO/sub 2/ interface is shown to affect carriers as if the bulk lifetime were reduced for a thin SOI, thus further improving the switching speed of IGBTs on thin (2- mu m) SOIs.<<ETX>>

New high voltage SOI device structure eliminating substrate bias effects

The breakdown voltage of a conventional SOI device is limited because it requires a thicker buried oxide as well as a thicker silicon layer. A new SOI device structure and its substrate are proposed to break through these constraints. The proposed new SOI is characterized by a SIPOS (Semi-Insulating POly-crystalline Silicon) layer inserted between the silicon layer and the buried oxide. Since the SIPOS layer effectively shields the influence of the substrate bias, 600 V breakdown voltage SOI diodes and lateral IGBTs were successfully realized using a 0.8 /spl mu/m SIPOS layer and 0.8 /spl mu/m buried oxide.

New 500V output device structures for thin silicon layer on silicon dioxide film

Studies into a 20 w deep trench technique for dielectric isolation and a high voltage lateral device structure for thin silicon layers have been carried out. These techniques can be applied to high voltage power ICs with high density packing. These proposed structures are characterized by a very shallow N-type diffusion layer on a bottom film of relatively thick silicon dioxide. Breakdown simulation was carried out by means of the two-dimensional device simulator TONADDEIIB. It was shown that a breakdown voltage of more than 500 V can be obtained with a 20 thick silicon layer structure.

200/spl deg/C high-temperature and high-speed operation of 440 V lateral IGBTs on 1.5 /spl mu/m thick SOI

This paper experimentally verifies that high-voltage lateral IGBTs fabricated on SOI of less than 5 /spl mu/m exhibit high switching speed without the need for any special device design. This paper also verifies, for the first time, that thin SOI is a promising candidate for 200/spl deg/C high-temperature operation, because switching speed does not deteriorate at high temperature.<<ETX>>

SOI device structures implementing 650 V high voltage output devices on VLSIs

It has been experimentally verified that 650 V breakdown voltage can be realized in lateral devices on a 14- mu m-thick SOI (silicon on insulator). The device structure is characterized by a shallow N-type diffusion layer on a 3- mu m-thick bottom oxide film. Trenches will be available for device isolation by using a thin SOI film for a power IC. The combination of high-voltage thin SOI device structures and the trench isolation technique will make VLSIs with high-voltage output devices possible.<<ETX>>

Ideal carrier profile control for high-speed switching of 1200 V IGBTs

A novel 1200 V Insulated Gate Bipolar Transistor (IGBT) for high-speed switching that combines Shorted Dummy-cell (SD) to control carrier extraction at the emitter side and P/P- collector to reduce hole injection from the backside is proposed. The SD-IGBT with P/P- collector has achieved 37 % reduction of turn-off power dissipation compared with a conventional Floating Dummy-cell (FD) IGBT. The SD-IGBT with P/P- collector also has high turn-off current capability because it extracts carriers uniformly from the dummy-cell. These results show the proposed device has a ideal carrier profile for high-speed switching.

Evaluation of 0.3.MU.m Poly-Silicon CMOS Circuits for Intelligent Power IC Application.

In this paper, we report on the fine device performance of a 0.3 µm gate length polysilicon complementary metal-oxide-semiconductor (CMOS). The breakdown voltage of 0.3 µm n-channel metal-oxide-semiconductor field effect transistor (NMOSFET) devices exceeds 6 V, which is higher than that of NMOSFET devices on separation by implanted oxygen (SIMOX) wafer. The drain current of a 10 µm channel width device is 540 µA, which is one-fifth of that of NMOSFET on SIMOX. The leakage current is less than 10-11 A/µm, when the gate voltage is below 0 V. The S-factor is 125 mV/dec, and the threshold voltage is 0.4 V. Therefore the ON/OFF current ratio is greater than 107. A delay time of 1 ns is achieved in polysilicon NAND rings. Hence, it is ascertained that the polysilicon CMOS is applicable for the fabrication of control and protection circuits on power devices.