Toshiyuki Naka

Analysis of GaN-HEMTs switching characteristics for power applications with compact model including parasitic contributions

In this paper, we report a newly developed compact model HiSIM-GaN [Hiroshima University STARC IGFET Model for GaN high electron mobility transistors (HEMTs)] including a capacitance model, which accurately captures the contributions originating from the devices field plate (FP) structure. The capabilities of the reported model are demonstrated by reproduction of the measured power efficiency of a boost converter circuit, enabled through separate extraction of the parasitic FP contributions. In addition, physical trap-density modeling is verified to be also of key importance for accurate prediction of the power efficiency.

Breakdown behaviour of high-voltage GaN-HEMTs

Abstract The breakdown mechanism of high-voltage GaN-HEMT was analysed using the experimental I–V characteristics and two-dimensional device simulation results. The holes are generated by the impact ionization under high applied voltage. A part of the generated holes accumulates beneath the gate and lowers the gate potential barrier. As a result, the source leakage current flowing over the gate potential increases rapidly and breakdown occurs. From these results, suppression of the impact ionization and the hole remove structure are effective for a highly reliable design concerning the breakdown.

10A 12V 1 chip digitally-controlled DC/DC converter IC with high resolution and high frequency DPWM

This paper introduces a 10 A 12 V single chip digitally-controlled DC/DC converter IC based on the low cost 0.6 um BiCD process. This IC includes the digital pulse width modulator (DPWM) module with the dead-time programmability. The average time resolution is 1.22 ns at the clock frequency 25 MHz on 0.6 um process. This resolution is as same as that for the counter-based DPWM with the clock frequency 817 MHz. The chip adopted low impedance metal bump technology for reducing a parasitic interconnection resistance in the power stage. The fabricated chip achieves a low on resistance 9.7 mOmega in the 20 V output LDMOS (@drain current=5 A, gate voltage=5 V). The maximum efficiency is 86.4% at output current 5 A when the input voltage, the output voltage and switching frequency and the dead-time are 12 V, 1.3 V, 780 KHz and 15 ns, respectively. The maximum voltage deviation and transient response time are 42 mV and 8 us, respectively in step-load (5 A to 10 A) transient response.

Switching controllability of high voltage GaN-HEMTs and the cascode connection

This paper reports that the switching controllability of high-voltage GaN-HEMTs and the cascode connection depends on the feedback capacitance design. The switching behavior of the GaN-HEMT can be controlled by the external gate resistance as the same manner as the conventional Si-MOSFETs. The switching controllability was improved by the substrate connection due to the parasitic capacitance change. The controllability of the cascode connection was slightly worse compared with the Si-MOSFET, because the effective feedback capacitance became small by the step by step switching operation.

ESD protection structure with novel trigger technique for LDMOS based on BiCD process

This paper presents ESD protection structure with novel trigger technique for LDMOS based on BiCD process. The proposed ESD protection element includes the same structure as drain region in Nch-LDMOS, the vertical NPN transistor and the lateral NPN transistor. The trigger voltage is depended on the breakdown voltage in the drain region integrated in ESD protection device and the avalanche current acts as the base current of NPN transistor. The high ESD current spreads to the buried layer in the vertical NPN transistor without locally concentrating in the drain edge. The value of the second breakdown trigger current It2 in the proposed ESD protection element is nearly four times as large as that in the simple LDMOS.

Optimization of 5V power devices based on CMOS for hot-carrier degradation

We propose “power CMOS,” suitable for use as large current output devices. The proposed structure can be fabricated by low cost 0.6um logic CMOS process and assures long-term reliability even under the stress of hot-electrons. The developed power CMOS have achieved low specific on resistances of 8.1m: mm 2 for NMOS and 21.1m: mm 2 for PMOS.

UIS withstanding capability and mechanism of high voltage GaN-HEMTs

This paper reports that the unclamped inductive switching (UIS) withstanding capability of high voltage GaN-HEMTs depends on the gate voltage at off-state and the substrate connection. The relation between the UIS withstanding capability and the electrical potential at gate and substrate is discussed by the results of the UIS test for GaN-HEMTs with p-type gate structure. Conclusively, the mechanism of UIS for the GaN-HEMT was clarified.

UIS test of high-voltage GaN-HEMTs with p-type gate structure

Abstract This paper reports the withstanding capability of unclamped inductive switching (UIS) of high voltage GaN-HEMTs as a function of the gate voltage in the off-state. One of the critical disadvantages of GaN-HEMTs is its lack of the UIS withstanding capability because of the non-removable structure of holes, which are generated by the avalanche breakdown. Therefore, a p-type GaN gate structure is attractive not only for normally-off operation but also for the UIS withstanding capability design from the viewpoint of hole-removal. This paper shows the results of the UIS test for GaN-HEMTs with the p-type gate structure. The UIS withstanding capability of GaN-HEMTs can be designed via the hole removal structure and the package thermal resistance.

Analysis of GaN high electron mobility transistor switching characteristics for high-power applications with HiSIM-GaN compact model

This paper presents a newly developed compact model HiSIM-GaN [Hiroshima University STARC IGFET Model for GaN high electron mobility transistors (HEMTs)]. The developed model includes two specific features of GaN-HEMT to reproduce the power efficiency accurately. One is the two-dimensional electron gas induced at the heterojunction, which is modeled by considering the potential distribution across the junction including the trap density contribution. The second feature is the field plate, which is introduced to delocalize the electric-field peak that occurs at the electrode edge. Using HiSIM-GaN, device characteristics have been simulated. It is demonstrated that measured DC/AC characteristics are well reproduced with the developed model. The model has also been applied to analyze circuit characteristics of a boost converter. It is shown that the waveform is well reproduced by considering one half of the trap density extracted with measured DC characteristics due to the time constant of trap events. Furthermore, it is verified that the power efficiency as a function of the load current is predicted within an accuracy of 1%. Influence of the trap density and the field plate on circuit performances is also discussed.

20A 5V single chip DC-DC converter IC with 5mohm MOSFET switch

In this paper, we demonstrate 20A operation and high switching frequency 980 KHz of single chip DC/DC converter. The fabricated chip consists of the digitally control block, the low on-resistance MOSFET switches and the drivers. The chip adopted low impedance metal bump technology. The on resistance of Nch MOSFET is 4.3m (@drain current=10A, gate voltage=5V) comparable to the discrete device. The fabricated chip achieves maximum output current 24A and max efficiency 91.2% for the input voltage, the output voltage and switching frequency of 5V, 1.083V and 980KHz, respectively. The efficiency without power loss by the parasitic resistance on PCB and output filter is 81.9% at the output current 20A.