Hanpei Koike

Demonstration, analysis, and device design considerations for independent DG MOSFETs

This paper describes a comprehensive study on the threshold voltage (V/sub th/) controllability of four-terminal-driven double-gate (DG) MOSFETs (4T-XMOSFETs) with independently switched DGs. Two types of 4T-XMOSFETs (fin and vertical) are experimentally demonstrated and their V/sub th/ controllability is thoroughly investigated in relation to the initial V/sub th/ in the DG-mode based on comprehensible modeling of the devices. Based on the investigation and simulated predictions, device design guidelines for 4T-XMOSFETs are proposed. Decreasing the workfunction of the DGs and increasing the oxide thickness of the second gate (T/sub ox2/) are preferable for improving the performance of the 4T-XMOSFET. The optimum workfunction of DGs for attaining low I/sub off(stand-by)/ and high I/sub on(active)/ under the limited V/sub g2/ condition is also proposed.

Design Optimization of FinFET Domino Logic Considering the Width Quantization Property

Design optimization of FinFET domino logic is particularly challenging due to the unique width quantization property of FinFET devices. Since the keeper device in domino logic is sized based on the leakage current of the pull-down network (PDN) (to meet the noise margin constraint), a reliable statistical framework is required to accurately estimate the domino gate leakage current. Considering the width quantization property, this paper presents such a statistical framework, which provides a reliable design window for keeper sizing to meet the noise margin constraint (for the practical range of threshold voltage variation in sub-32-nm technology nodes). On the other hand, the width quantization property restricts the design optimization (including power/performance characteristics) typically achieved via continuous keeper sizing in planar-CMOS domino logic designs. To cope with this restriction, this paper also introduces a novel methodology for FinFET-based keeper design, which exploits the exclusive property of FinFET devices (capacitive coupling between the front gate and the back gate in a four-terminal FinFET) to simultaneously achieve higher performance and lower power consumption. Using this new methodology, the keeper device is made weaker at the beginning of the evaluation phase to reduce its contention with the PDN, but gradually becomes stronger to provide a higher noise margin.

Performance and yield enhancement of FPGAs with within-die variation using multiple configurations

A new method for improving the timing yield of field-programmable gate array (FPGA) devices affected by random within-die variation is proposed. By selection of an appropriate configuration from a set of functionally equivalent configurations such that the critical paths do not share same circuit resources on the FPGA, both the average critical path delay and its standard deviation are reduced substantially under conditions of large random variation. Large within-die variations of device parameters such as transistor threshold voltage are anticipated in future semiconductor technologies, resulting in degradation of parametric yields. Comparing to the previous approach which compensates for such within-die variation by designing circuit placement for each chip using variation information measured before, our method does not require the measurement of process variations and execution of design tools for each chip. The average critical path delay is reduced by up to 5% assuming 30% (σ/μ) variation in threshold voltage, with a corresponding 50% decrease in standard deviation.

Characterization of metal-gate FinFET variability based on measurements and compact model analyses

A FinFET compact model, which provides physical representation of measurement data, was developed and was successfully applied to the characterization of sate-of-the-art metal-gate (MG) FinFETs. By combining the transistor size measurement and the model parameter calibration, the Vth variation of the MG FinFETs was analyzed into structure-based (TSi, LG) and material-based (gate work-function) variations for the first time. In addition, the extracted variations were incorporated into the compact model, and FinFET SRAM variability for hp-32-nm node was predicted.

Suppression of Intrinsic Delay Variation in FPGAs using Multiple Configurations

A new method for improving the timing yield offield-programmable gate array (FPGA) devices affected by intrinsicwithin-die variation is proposed. The timing variation is reducedby selecting an appropriate configuration for each chip from a setof independent configurations, the critical paths of which do notshare the same circuit resources on the FPGA. In this article, theactual method used to generate independent multiple configurationsby simply repeating the routing phase is shown, along with theresults of Monte Carlo simulation with 10,000 samples. Onesimulation result showed that the standard deviations of maximumcritical path delays are reduced by 28% and 49% for 10% and 30%Vth variations (σ/ μ), respectively,with 10 independent configurations. Therefore, the proposed methodis especially effective for larger Vth variation and isexpected to be useful for suppressing the performance variation ofFPGAs due to the future increase of parameter variation. Anothersimulation result showed that the effectiveness of the proposedtechnique was saturated at the use of 10 or more configurationsbecause of the degradation of the quality of the configurations.Therefore, the use of 10 or fewer configurations is reasonable.

Metal-Gate FinFET Variation Analysis by Measurement and Compact Model

A compact model (CM) for fin-type FETs (FinFETs) was successfully developed and applied to variability analysis of a fabricated state-of-the-art metal-gate (MG) FinFET. By combining the statistical measurements with the CM calibration, V th variation was, for the first time, broken down into structure-based (silicon fin thickness and gate length) and material-based (gate work function) components. As a result, the measured variation of MG FinFET performance was successfully reproduced by the CM. Characterization using the CM with the measured statistical data provides insight on the gate work function variation of 16 meV in short-channel molybdenum (Mo) gate FinFETs.

A Dynamical Power-Management Demonstration Using Four-Terminal Separated-Gate FinFETs

Dynamically power-controllable CMOS inverters have been successfully demonstrated using separated-gate four-terminal (4T) FinFETs. The threshold voltages of the both pMOS and nMOS FinFETs can be flexibly controlled by applying a bias voltage to the control-gate. We demonstrate for the first time that the power consumption of the CMOS inverter can be dynamically controlled using the variable threshold voltage provided by the 4T-FinFET. These results strongly suggest the advantage of the power-managed CMOS circuits using 4T-FinFETs

XDXMOS: a novel technique for the double-gate MOSFETs logic circuits - to achieve high drive current and small input capacitance together

A novel technique for the double-gate MOSFETs digital circuit, called cross-drive XMOS (XDXMOS), is proposed. Detailed mixed-mode circuit and device simulation results show that, with a simple addition of a register to the double-gate device in the 4-terminal operation mode, XDXMOS can achieve high drive current and small input capacitance together, and that 45% better power consumption performance and 25% better operation speed performance improvement over the conventional 3-terminal operation mode can be attained, while maintaining the ability for such useful techniques as the multiple-Vt method and the adaptive Vt control.

Fully-functional FPGA prototype with fine-grain programmable body biasing

A fully-functional FPGA prototype chip in which the programmable body bias voltage can be individually applied to elemental circuits such as MUXes, LUT and DFF is fabricated using low-power 90-nm bulk CMOS technology and the area overhead, dynamic current, static current and operational speed are evaluated in silicon. In measurements, 10 ISCAS benchmark circuits are implemented by employing newly developed CAD tools which consist of VT mapper as well as placer and router. Mask layout shows that well-separated margins, programmable body bias circuits, and additional configuration memories occupy 54% of the FPGA tile area. Measurement results show that the fabricated FPGA reduces the static current by 91.4% in average. In addition, evaluations by implementing ring oscillator with various body bias voltage pairs demonstrate the static current reduction from 23.1 uA to 1.0 uA by assigning low threshold voltage and high threshold voltage to MOSFETs on a critical path and the rest of the MOSFETs, respectively while maintaining the same oscillation frequency of 6.6 MHz as the frequency when all MOSFETs are assigned low threshold voltage. Moreover the fine-grain programmable body bias technique accelerates the oscillation frequency of ring oscillator implemented on FPGA by aggressively applying forward body bias voltage, while assignment of HVT to MOSFETs on the non-critical path by applying the reverse body biasing effectively suppresses exponential increase of static current caused by the forward body biasing.

Optimal set of body bias voltages for an FPGA with field-programmable V/sub th/ components

An FPGA with field-programmable Vth components can attain both high performance and low power consumption, without placement and routing constraints, by flexibly controlling the threshold voltage (Vth) of transistors. Since Vth for transistors for a specific circuit block in an FPGA is chosen from a set of Vth values defined by body bias voltage set (BBVS), adequate selection of BBVS is important in the design decision process in a field-programmable Vth method. In this paper, the effect of the selection of BBVS on static power reduction in an FPGA with field-programmable Vth components was presented. To select the optimal BBVS among several supplied body bias voltage candidates, several BBVSs are provided. The results show that the best BBVS achieves remarkable static power reduction, to as little as 1/30 the value in a conventional FPGA without performance degradation. In addition, the study on the optimal selection of body bias voltage for high-Vth transistor in a BBVS reveals that deep reverse body bias for high-Vth transistor does not necessarily offer the optimal condition, and optimization is necessary