Kenichi Yasuda

A mixed-mode voltage down converter with impedance adjustment circuitry for low-voltage high-frequency memories

This paper proposes a low voltage operation technique for a voltage down converter (VDC) using a mixed-mode VDC (MM-VDC), that combines an analog VDC and a digital VDC, and provides high frequency application using an impedance adjustment circuitry (IAC). The MM-VDC operates with a small response delay and a large supply current. Moreover, the IAC is adopted by the MM-VDC for wide range frequency operation under low voltage conditions. The IAC can change the supply current capability in accordance with the load operation frequency to avoid the overshoot and undershoot problems caused by the unmatched supply current. A 64 Mb-DRAM test device operated with the MM-VDC achieves well-controlled internal voltage (VCI) level and achieves high frequency operation. These systems, the MM-VDC and the IL-VDC, can be applicable for both low voltage and high frequency operation.

An automatic temperature compensation of internal sense ground for subquarter micron DRAM's

This paper describes DRAM array driving techniques and the parameter scaling techniques for low voltage operation using the boosted sense ground (BSG) scheme and further improved methods. Temperature compensation and adjustable internal voltage levels maintain a small subthreshold leakage current for a memory cell transistor (MC-Tr), and a distributed BSG (DBSG) scheme and a column decoded sensing (CDS) scheme achieve the effective scaling. These schemes can set the DRAM array free from the leakage current problem and the influence of temperature variations. Therefore, parameters for the MC-Tr, threshold voltage (V/sub th/), and the boosted voltage for the gate bias can be scaled down, and it is possible to determine the V/sub th/ of the MC-Tr simply (0.45 V at K=0.4) for the satisfaction of the small leakage current, for high speed and stable operation, and for high reliability (V/sub PP/ is below 2 V/sub CC/). They are applicable to subquarter micron DRAMs of 256 Mb and more. >

An Automatic Temperature Compensation Of Internal Sense Ground For Sub-quarter Micron Drams

This paper describes DRAM array driving techniques and the parameter scaling techniques for a low voltage operation using the boosted sense ground (BSG) scheme andfurther improved methods. A temperature compensation and adjustable internal voltage levels maintain a small subthreshold leakage current of a memory cell transistor (MC-Tr), and a distributed BSG (DBSG) scheme and a column decoded sensing (CDS) scheme achieve the effective scaling. These schemes can set the DRAM array free from a leakage current problem and free them from an influence of temperature variations. Therefore, parameters for the MC-Tr, threshold voltage (V th ), and the boosted voltage for the gate bias can be scaled down, and it is possible to determine the V th of the MC-Tr easy (0.45 V at K = 0.4) for the satisfaction of the small leakage current, for the high speed and stable operation, and for the high reliability (V PP is below 2 V CC ). They are applicable to the subquarter micron DRAMs of 256 Mb and more

A mixed-mode voltage-down converter with impedance adjustment circuitry for low-voltage wide-frequency DRAMs

In DRAMs a dramatic operation voltage reduction has been realized by the voltage-down converter (VDC) for a low power dissipation and high reliability. However, in the low-voltage and high-frequency domain this technique will see several crucial problems. Besides, the wide-frequency operation (e.g. an extended data output and a synchronous operation) and the variable-load current (e.g, a variable refresh cycle and a changeable data output) are required. This paper proposes VDC circuit techniques for the low-voltage (less than 2.5 V), wide-frequency, and the variable-load current. The mixed-mode VDC (MM-VDC) provides two-modes of current by the analog VDC (A-VDC) and the digital VDC (D-VDC) supply being suitable for the load current. It also reduces the current consumption in the VDC and guarantees stable operation. Moreover, the impedance adjustment circuitry (IAC) controls the current supply capability of the D-VDC according to the load operation frequency to minimize the bounce of the internal power supply level. The MM-VDC can be applicable to low-voltage wide-frequency DRAMs.