Hideyuki Ozaki

A 288-kb fully parallel content addressable memory using a stacked-capacitor cell structure

A 288-kb (8 K words*36 b) fully parallel content addressable memory (CAM) LSI using a compact dynamic CAM cell with a stacked-capacitor structure and a novel hierarchical priority encoder is described. The stacked-capacitor structure results in a very compact dynamic CAM cell (66 mu m/sup 2/) which is operationally stable. The novel hierarchical priority encoder reduces the circuit area and power dissipation. In addition, a new priority decision circuit is introduced. The chip size is 10.3 mm*12.0 mm using a 0.8- mu m CMOS process technology. A typical search cycle time of 150 ns and a maximum power dissipation of 1.1 W have been obtained using circuit simulation. In fabricated CAM chips, the authors have verified the performance of a search operation at a 170-ns cycle and have achieved a typical read/write cycle time of 120 ns. >

An efficient back-bias generator with hybrid pumping circuit for 1.5-V DRAMs

An efficient back-bias (V/sub bb/) generator with a newly introduced hybrid pumping circuit (HPC) is described. This system attains a V/sub bb/ level of /spl minus/1.44 V at V/sub cc/=1.5 V, compared to a conventional system in which V/sub bb/ only reaches /spl minus/0.6 V. HPC can pump without the threshold voltage (V/sub th/) loss that conventional systems suffer. HPC is indispensable for 1.5-V DRAMs, because a V/sub bb/ level lower than /spl minus/1.0 V is necessary to meet the limitations of the V/sub th/, of the access transistor. HPC uses one NMOS and one PMOS pumping transistor. By adopting a triple-well structure at the pumping circuit area, the NMOS can be employed as a pumping transistor without minority carrier injection. >

A redundancy test-time reduction technique in 1-Mbit DRAM with a multibit test mode

To realize an efficient redundancy test using the multibit test (MBT) mode, a redundancy flag on a memory LSI tester and an effective redundancy technique which cooperates with the MBT mode have been introduced. This simple redundancy architecture needs only the RFLG (512 bits for the 1 M*1-bit DRAM) as a hardware option on a memory LSI tester. The program development time for the redundancy test has been shortened. Throughput improvement of six to ten times has been achieved in the actual 1-Mb DRAM redundancy test. >

An adjustable output driver with a self-recovering Vpp generator for a 4M/spl times/16 DRAM

An adjustable output driver with a self-recovering Vpp generator for a 4 M/spl times/16 DRAM (dynamic random-access memory) is presented. Its driver characteristics can easily be changed between fast mode and slow mode in the assembly process. The driver with a small inductance load operates 2.5 ns faster in fast mode than in slow mode, and the driver in slow mode reduces the initial drive current and prevents ringing waveforms even with large inductance load. With a 5 pF capacitance load and 20 cm wire, the ringing amplitude in slow mode is reduced to 1/3 that of the fast mode. Users can choose the operation mode of the output driver according to their application. The self-recovering Vpp generators feed 16 output drivers and control the generator capacity according to the data pattern to supply the same amount of Vpp charge consumed by output drivers. The Vpp generator saves 3.9 mA on average at a 25 ns read cycle.

A low power and high speed data transfer scheme with asynchronous compressed pulse width modulation for AS-Memory

We propose a high speed and low power data transfer scheme for the wide internal data bus of an AS-Memory using the asynchronous compressed pulse width modulation (AC-PWM) technique and an automatic gain controlled (AGC) amplifier. The maximum bit rate per bus of AC-PWM increases by 12 times that of the conventional 100MHz data bus. The AGC amplifier achieves a fast data output while reducing by 1/3 the standby current. The proposed architecture is a key advance in the future development of AS-Memories.

Semiconductor memory device with a laser programmable redundancy circuit

A semiconductor memory device with a laser programmable redundancy circuit, which includes: a plurality of decoders for selecting a row or column of the memory; at least one spare decoder which is selected instead of a decoder connected to a faulty memory cell; a link element inserted in series with the precharging transistor and connected between the power supply and the decoder output line; a signal generator which generates a non-selection signal for making the object decoder unselected only when a spare decoder is selected, the signal generator being provided in the spare decoder; and a transistor, having a gate to which the non-selection signal is input, with the drain and the source thereof being connected to the decoder output and ground, respectively, the transistor being provided in the decoder.

A mixed-mode voltage down converter with impedance adjustment circuitry for low-voltage high-frequency memories

This paper proposes a low voltage operation technique for a voltage down converter (VDC) using a mixed-mode VDC (MM-VDC), that combines an analog VDC and a digital VDC, and provides high frequency application using an impedance adjustment circuitry (IAC). The MM-VDC operates with a small response delay and a large supply current. Moreover, the IAC is adopted by the MM-VDC for wide range frequency operation under low voltage conditions. The IAC can change the supply current capability in accordance with the load operation frequency to avoid the overshoot and undershoot problems caused by the unmatched supply current. A 64 Mb-DRAM test device operated with the MM-VDC achieves well-controlled internal voltage (VCI) level and achieves high frequency operation. These systems, the MM-VDC and the IL-VDC, can be applicable for both low voltage and high frequency operation.

Cell-plate-line and bit-line complementarily sensed (CBCS) architecture for ultra low-power non-destructive DRAMs

In order to develop very high density DRAMs, the reduction of memory-array current, accounting for over 80% of total chip current, must be given serious consideration. As the number of activated sense-amplifiers (SAs) increase, the amount of consumed charge on bit-lines (BLs) increases accordingly. This paper describes a novel circuit design, called Cell-Plate-Line and Bit-Line Complementarily Sensed (CBCS) Architecture. Only the selected SA of a whole array is activated, thereby reducing array read/write current to below 1% compared with conventional ones. Furthermore, refresh operation can easily be executed and the array refresh current is reduced to below 50% without loss of the read-out differential signal.

An efficient charge recycle and transfer pump circuit for low operating voltage DRAMs

An efficient Vpp generator with a charge recycle pump and a charge transfer pump have been proposed. The charge recycle operation can reduce the Vpp generating current by 38% without decreasing the Vpp supply current. The charge transfer operation enables the generation of the Vpp supply current at over the 2/spl middot/Vcc level. These techniques are highly effective in low voltage DRAMs.

Cell-plate-line/bit-line complementary sensing (CBCS) architecture for ultra low-power DRAMs

In the realization of gigabit scale DRAMs, one of the most serious problems is how to reduce the array power consumption without degradation of the operating margin and other characteristics. This paper proposes a new array architecture called cell-plate-line/bit-line complementary sensing (CBCS) architecture which realizes drastic array power reduction for both read/write operations and refresh operations, and develops a large readout voltage difference on the bit-line and cell-plate-line. For read/write operations, the array power reduces to only 0.2%, and for refresh operations becomes 36%, This architecture requires no unique process technology and no additional chip area. Using a test device with a 64-Mb DRAM process, the basic operation has been successfully demonstrated. This new memory core design realizes a high-density DRAM suitable for the 1-Gb level and beyond with power consumption significantly reduced.