Mikio Asakura

A circuit design of intelligent CDRAM with automatic write back capability

The authors describe a unique intelligent memory based on a distributed CDRAM (cache DRAM) architecture, which consists of three hierarchical memory sections, DRAM, SRAM, and CAM, that constitute on-chip TAG. This architecture provides a high-performance intelligent main memory and a pin compatibility with high-speed address nonmultiplexed memories (DRAM, SRAM, and pseudo-SRAM). This RAM can be fabricated by the standard CMOS DRAM process with little area penalty. The intelligent CDRAM with an automatic write-back function can realize a short average read/write cycle time. The write-back operation without a complex controller minimizes the write cycle time drastically compared with write through

A 34ns 16MbDRAM with controllable voltage down convertor

The centrally active cholinesterase inhibitor physostigmine induces a behavioral syndrome which is thought to represent a model of spontaneous depression. In the present acute trial in 6 healthy volunteers, this model depression was accompanied by clearcut cardiovascular, metabolic and neuroendocrine phenomena of stress. The extent of the changes from baseline, however, scarcely correlated between the behavioral and physiologic phenomena. The behavioral and physiological phenomena could not be antagonized by brofaromine, a putative antidepressant reversibly and selectively inhibiting monoamine oxidase A (MAO-A), contrasting to the complete inhibition by the central cholinolytic scopolamine. This is further evidence that antidepressant efficacy depends on long-term adaptive changes secondary to the enhancement of aminergic neurotransmission rather than this enhancement itself.

A smart design methodology for advanced memories

The authors propose a smart design methodology for advanced memories to reduce the turn around time for circuit revisions with no area penalty. This method was applied to the development of 16 Mb DRAM with double metal wiring. The turn around time can be reduced to 1/8 by 1500 gates of extra n-ch and p-ch transistors under the power line and the signal line. This design methodology is confirmed to be very effective.<<ETX>>