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Dive into the research topics where Kenji Fukuzono is active.

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Featured researches published by Kenji Fukuzono.


electronic components and technology conference | 2006

High-performance flip-chip BGA technology based on thin-core and coreless package substrate

Masateru Koide; Kenji Fukuzono; H. Yoshimura; Toshihisa Sato; K. Abe; Hidehiko Fujisaki

A new organic build-up substrate packaging technology was developed in Fujitsu for high-end servers, where lower V-G impedance on substrate and thermal resistance are realized by applying metallic thermal injection materials. In the present paper, two important accomplishments in assembling process, eliminating voids with metallic thermal injection and controlling substrate flatness on mounting large LSIs, are investigated, and evaluated


electronic components and technology conference | 2012

Low warpage coreless substrate for large-size LSI packages

Mamoru Kurashina; Daisuke Mizutani; Masateru Koide; Manabu Watanabe; Kenji Fukuzono; Hitoshi Suzuki

Due to inadequate rigidity, warpage of coreless substrates is generally large compared to other types of LSI package substrates. Therefore, the most important problem in the application of coreless substrates is warpage reduction during the reflow process. So far, there have been only a limited number of reports on coreless substrates for large-size LSI packages. Moreover, there have been very few examples that discussed substrate layer structure designs for warpage reduction and reliability improvement in the LSI assembly process. In the present study, we focus on developing coreless packages for large-size LSIs. To achieve our goal, we adopted the following development processes. First, we designed analytical models with different layer structures comprising two kinds of materials, and investigated the effect of layer structure on warpage reduction using warpage simulations. Next, we made four kinds of real coreless substrates with layer structures identical to the simulation models, and verified the actual thermal warpage behavior. Finally, we investigated the thermal stress reliabilities of these substrates after LSI mounting. From the results, we found that warpage reduction and reliability enhancement of coreless substrates were realized by arranging the high rigidity materials on the external layers of the substrates.


electronic components and technology conference | 2014

Development of second-level connection method for large-size CPU package

Shunji Baba; Masateru Koide; Manabu Watanabe; Kenji Fukuzono; Tsuyoshi Yamamoto; Seiki Sakuyama; Kozo Shimizu; Keishiro Okamoto; Daisuke Mizutani

This paper reports on second-level interconnection development for a large-scale Ball Grid Array (BGA) package. Generally, control of warpage becomes a problem as BGA packages become larger. To solve this problem, the following two measures were executed. The first was adoption of a low-temperature solder, and the second was warpage control using a heat spreader as a fixture. We were able to decrease the reflow temperature to 200°C by applying the low-temperature solder, and the effect was a warp reduction of 200 μm. Moreover, the shape of the heat spreader was optimized through a thermal-stress simulation, obtaining a warp reduction of 100 μm. Verification with a test vehicle was executed, no short/opening was observed, and the results of a thermal cycle test and simulation confirmed there was no problem in reliability.


electronic components and technology conference | 2017

Development of Large Size CPU Package Structure Using Embedded Thin Film Capacitor Package Substrate

Kenji Fukuzono; Manabu Watanabe; Daisuke Mizutani; Tomoyuki Akahoshi; Hidehiko Fujisaki; Seigo Yamawaki; Kei Fukui

This paper reports on a large-size CPU package for UNIX servers which employs embedded thin film capacitor layers. The substrate of this package has two thin film capacitor layers in the surface of the core layer, which has a capacitance of 25 uF in total. In order to adopt this package substrate, we confirmed the effect of the thin film capacitor layers on the package assembly process. We actually measured mechanical characteristics and the coefficient of thermal expansion (CTE), and confirmed that we can use it like conventional package substrates. This package has passed the preprocessing and subsequent environmental test on JEDEC Level 4, and we think that a high-quality package has been developed this time. Fujitsu adopted a low melting point solder BGA from a previous-generation package. Its composition is Sn-57Bi-1.0Ag. However, this solder has an issue with deformation after a low-temperature reflow profile for the solder ball attachment process on the package. In this work, we were able to find the cause of this phenomenon, and by changing the Ag content from 1.0% to 0.4%, we achieved a complete low-temperature assembly process. In addition, BGA connection reliability was confirmed.


Archive | 2006

Layered board and manufacturing method of the same, electronic apparatus having the layered board

Takashi Kanda; Kenji Fukuzono; Manabu Watanabe


Archive | 2004

Packaging method, packaging structure and package substrate for electronic parts

Masateru Koide; Misao Umematsu; Takashi Kanda; Yasuhiro Usui; Kenji Fukuzono


Archive | 2004

Semiconductor device having stiffener

Takashi Kanda; Kenji Fukuzono


Archive | 2010

Semiconductor device and heat radiation member

Kenji Fukuzono


Archive | 2009

Printed circuit board unit and semiconductor package

Kenji Fukuzono; Hideaki Yoshimura


Archive | 2005

Electronic component package including joint material for higher heat conductivity

Naoaki Nakamura; Hideaki Yoshimura; Kenji Fukuzono; Toshihisa Sato

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