Tomoko Monda

Large-Scale Damage Path Simulation for Solder Joints in a BGA Package

There is high demand for fatigue life prediction of solder joints in electronic packages such as ball grid arrays (BGAs). A key component of fatigue life prediction technology is a canary device, which warns of the impending risk of failure through loss of function before other important parts become severely impaired. In a BGA package, thermal fatigue of solder joints normally starts from the solder joints at the outermost part of the package. This can be taken advantage of by using the outermost solder joints as canary devices for detecting the degree of cumulative mechanical fatigue damage. To accurately estimate the lifetimes of other functional solder joints, it is essential to understand the relationship between the fatigue lives of canary joints and other functional joints. Damage path simulation is therefore proposed for predicting the crack propagation in solder joints on electronic packages through numerical simulation. During the process of designing the layout of canary joints and other joints, it is very useful to know not only the relationship between the fatigue lives of the canary and other joints, but also the path of crack propagation through all joints. This paper presents a method for estimating the relationship between the fatigue lives of canary joints and other joints by using damage path simulation. Some BGA packages mounted on a printed circuit board are modeled to demonstrate the process of estimating the lifetime of each joint under thermal cycle loading. A large-scale finite element model is used to accurately represent the geometrical properties of the printed circuit board and package. Both crack initiation and crack propagation processes can be simultaneously evaluated by modeling all of the solder joints on each package. The results show that damage path simulation and large-scale modeling are useful for determining the layout of canary joints in electronic packages.Copyright

Prognostic Health Monitoring Method for Fatigue Failure of Solder Joints on Printed Circuit Boards Based on a Canary Circuit

Continuing improvements in both capacity and miniaturization of electronic equipment such as solid state drives (SSDs) are spurring demand for high-density packaging of NAND-type flash memory mounted on SSD printed circuit boards. High-density packaging leads to increased fatigue failure risk of solder joints due to the decreased reliability margin for stress. We have developed a failure precursor detection technology based on fatigue failure probability estimation during use. This method estimates the cycles to fatigue failure of an actual circuit by detecting broken connections in a canary circuit (a dummy circuit of daisy-chained solder joints). The canary circuit is designed to fail earlier than the actual circuit under the same failure mode by using accelerated reliability testing and inelastic stress simulation. The statistical distribution of the strain range of solder joints can be provided by Monte Carlo simulations based on the finite element method and random load modeling. A feasibility study of the failure probability estimation method is conducted by applying the method to a printed circuit board on which a ball grid array (BGA) package is mounted using BGA solder joints. The proposed method is found to be useful for prognostic health monitoring of solder joint’s fatigue failure.© 2013 ASME