Kenji Mukaida

A Passive UHF RF Identification CMOS Tag IC Using Ferroelectric RAM in 0.35-

A passive UHF RF identification (RFID) tag IC with embedded 2-KB ferroelectric RAM (FeRAM) for rewritable applications enables a 2.9 times faster read-and-write transaction time over EEPROM-based tag ICs. The resulting FeRAM-based tag has a nominally identical communication range for both read and write operations, which is indispensable for data write applications. The evaluated tag communication range with a folded dipole antenna is from 0 m to 4.3 m, at the 953-MHz carrier frequency with 4-W transmitting Effective Isotropic Radiated Power (EIRP) from a reader/writer. The developed tag IC features two circuit blocks to maximize the communication range in 0.35-mum CMOS/FeRAM technology. First is a CMOS-only full-wave rectifier, which can improve the measured efficiency by up to 36.6% by reducing the input parasitic capacitances and optimization of multiplier structure. This efficiency is more than twice that of previously-published results. Second is a low-voltage current-mode ASK demodulator to accommodate a low-breakdown voltage of FeRAM, which converts the ASK power modulation into a linearly modulated current over an incoming power range of 27 dB, corresponding to the entire communication range. The developed demodulator can thus resolve the primary design tradeoff issue between device protection and detection sensitivity in the conventional voltage-mode demodulator

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A passive UHF RFID tag LSI in 0.35mum CMOS with 2kb FeRAM enables the 2.9-times higher 32b read-and-write throughput over an EEPROM-based tag. A CMOS full-wave rectifier improves the power efficiency from 16.6% up to 36.6% by lossless internal Vth cancellation and mirror stack architecture. A current-mode ASK demodulator converts the 15% power modulation into linear current signal over a 27dB dynamic range of the incoming power

Technology

Circuit techniques to realize unlimited program cycle operation in ferroelectric nonvolatile (NV) SRAM have been developed with conventional ferroelectric materials. Program operation is separated into volatile write operation without polarization change and nonvolatile store operation with polarization change. Biasing of the memory cell is optimized to meet reliability requirements. The developed circuit principle is extended to implement a low-power nonvolatile flip-flop applicable to long communication range radio frequency identification tag LSIs.

A Passive UHF RFID Tag LSI with 36.6% Efficiency CMOS-Only Rectifier and Current-Mode Demodulator in 0.35/spl mu/m FeRAM Technology

A nonvolatile ferroelectric SRAM based 8-context dynamically programmable gate array enables low-cost field programmable systems by the elimination of off-chip nonvolatile memories. Read and program procedures of the associated configuration memory are securely protected, so that unauthorized users cannot gain access to configuration data. The ferroelectric SRAM configuration memory features 2ns nondestructive read operations along with stable data recall. The logic block circuit is optimized to improve available logic gates for multi-context scheme.

Design and applications of ferroelectric nonvolatile SRAM and flip-flop with unlimited read/program cycles and stable recall

High-speed and area-efficient Montgomery modular multipliers for RSA algorithm has been developed for digital signature and user authentication in high-speed network and smart card systems. Multiplier-accumulator (MAC) in the developed Montgomery modular multiplier has non-identical multiplicand/multiplier word length. This organization eliminates the bottleneck in memory bandwidth, and enables to use single-port memory for area and power reductions. The developed MAC is faster than the common word length organization due to short critical path. 5,000 digital signature productions/sec is obtained with a three-stage pipelined architecture in 0.18 /spl mu/m CMOS technology.

A ferroelectric memory-based secure dynamically programmable gate array

A nonvolatile ferroelectric SRAM based 8-context dynamically programmable gate array enables low-cost field programmable systems by the elimination of off-chip nonvolatile memories. Read and program procedures of the associated configuration memory are securely protected, so that unauthorized users cannot gain access to configuration data. The ferroelectric SRAM configuration memory features 2ns nondestructive read operations along with stable data recall. The logic block circuit is optimized to improve available logic gates for multi-context scheme.

Design of high-speed and area-efficient Montgomery modular multiplier for RSA algorithm

High-speed, area-efficient, and low-power Montgomery modular multipliers for RSA algorithm have been developed for digital signature and user authentication in high-speed network systems and smart card LSIs. The multiplier-accumulators (MAC) in the developed Montgomery modular multipliers have a non-identical multiplicand/multiplier word length organization. This organization can eliminate the bandwidth bottleneck associated with a data memory, and enables to use a single-port memory for area and power reductions. The developed MAC is faster than the conventional identical word length organization due to the shortened critical path. For smart card applications, an area-efficient architecture with 42 kgates can produce 1.2 digital signatures in a second for 2,048-bit key length with the power consumption of 6.8 mW.