Hajime Kurata

A Passive UHF RF Identification CMOS Tag IC Using Ferroelectric RAM in 0.35-

A passive UHF RF identification (RFID) tag IC with embedded 2-KB ferroelectric RAM (FeRAM) for rewritable applications enables a 2.9 times faster read-and-write transaction time over EEPROM-based tag ICs. The resulting FeRAM-based tag has a nominally identical communication range for both read and write operations, which is indispensable for data write applications. The evaluated tag communication range with a folded dipole antenna is from 0 m to 4.3 m, at the 953-MHz carrier frequency with 4-W transmitting Effective Isotropic Radiated Power (EIRP) from a reader/writer. The developed tag IC features two circuit blocks to maximize the communication range in 0.35-mum CMOS/FeRAM technology. First is a CMOS-only full-wave rectifier, which can improve the measured efficiency by up to 36.6% by reducing the input parasitic capacitances and optimization of multiplier structure. This efficiency is more than twice that of previously-published results. Second is a low-voltage current-mode ASK demodulator to accommodate a low-breakdown voltage of FeRAM, which converts the ASK power modulation into a linearly modulated current over an incoming power range of 27 dB, corresponding to the entire communication range. The developed demodulator can thus resolve the primary design tradeoff issue between device protection and detection sensitivity in the conventional voltage-mode demodulator

\mu{\hbox {m}}

A passive UHF RFID tag LSI in 0.35mum CMOS with 2kb FeRAM enables the 2.9-times higher 32b read-and-write throughput over an EEPROM-based tag. A CMOS full-wave rectifier improves the power efficiency from 16.6% up to 36.6% by lossless internal Vth cancellation and mirror stack architecture. A current-mode ASK demodulator converts the 15% power modulation into linear current signal over a 27dB dynamic range of the incoming power

Technology

We propose a new method to control the threshold voltages (V/sub th/) in sub-0.2 /spl mu/m MOSFETs. The method suppresses V/sub th/ fluctuations caused by variations in the fabricated gate length. Our scheme is to change the concentration of the channel impurity according to the gate length by tilted ion implantation from two directions after the polysilicon gate formation. We show the feasibility of our process by two-dimensional (2-D) process and device simulations. Then we clarify that our scheme was realized in fabricated nMOSFETs. We also measured the V/sub th/ in numerous MOSFETs and show that our method can indeed suppress V/sub th/ fluctuations caused by variations in the fabricated gate length.

A Passive UHF RFID Tag LSI with 36.6% Efficiency CMOS-Only Rectifier and Current-Mode Demodulator in 0.35/spl mu/m FeRAM Technology

We investigated the impart of shallow source/drain (S/D) on the characteristics of short-channel pMOSFETs with a gate length of 0.1 /spl mu/m. We fabricated an ultrashallow S/D junction by solid phase diffusion of boron from a BSG sidewall. By precisely estimating the effective channel length, we found that the threshold voltage roll-off is independent of junction depth. In addition, the current drivability is degraded in a sample with a shallow junction. This makes it clear that a shallow junction with a low surface concentration does not improve the overall characteristics of ultrasmall pMOSFETs.

Self-aligned control of threshold voltages in sub-0.2-/spl mu/m MOSFETs

The impact ionization rate in a silicon metal-oxide-semiconductor field-effect transistor (MOSFET) is universally plotted on a simple straight line when ln(I sub/I d) is plotted versus 1/(V ds-V dsat). V dsat is the drain saturation voltage. However, we found a deviation from this universal relationship for different gate voltages applied to the MOSFETs fabricated by 0.15 µ m technology. We show that the deviation is due to the gate-voltage dependence of the saturation electric field E sat, which results from the degradation of the effective surface mobility µ eff. The new method for finding a universal relationship is proposed.

Impact of shallow source/drain on the short-channel characteristics of pMOSFETs

In this paper, we describe our triple sidewall spacer scheme to achieve 45 nm ground rule for high-performance applications. This triple sidewall spacer scheme uses three kinds of sidewall spacers, in which the first sidewall is used for the source/drain extension implantation offset (SW1), the second is for the p-channel field effect transistor (PFET) embedded silicon germanium offset (SW2), and the third spacer is for the deep source/drain implantation offset (SW3). We also evaluated the impact of sidewall spacer materials and structures on device characteristics. After optimizing each sidewall spacer material and structure including offset width, we successfully demonstrated identical device characteristics with the minimum poly-pitch layout while minimizing layout dependence. This sidewall spacer scheme has the capability to achieve the 45 nm ground rule, and our sidewall spacer design is mature and suitable for 45-nm-node high-performance applications.