Shoichi Masui

Experimental results and modeling techniques for substrate noise in mixed-signal integrated circuits

An experimental technique is described for observing the effects of switching transients in digital MOS circuits that perturb analog circuits integrated on the same die by means of coupling through the substrate. Various approaches to reducing substrate crosstalk (the use of physical separation of analog and digital circuits, guard rings, and a low-inductance substrate bias) are evaluated experimentally for a CMOS technology with a substrate comprising an epitaxial layer grown on a heavily doped bulk wafer. Observations indicate that reducing the inductance in the substrate bias is the most effective. Device simulations are used to show how crosstalk propagates via the heavily doped bulk and to predict the nature of substrate crosstalk in CMOS technologies integrated in uniform, lightly doped bulk substrates, showing that in such cases the substrate noise is highly dependent on layout geometry. A method of including substrate effects in SPICE simulations for circuits fabricated on epitaxial, heavily doped substrates is developed. >

A Passive UHF RF Identification CMOS Tag IC Using Ferroelectric RAM in 0.35-

A passive UHF RF identification (RFID) tag IC with embedded 2-KB ferroelectric RAM (FeRAM) for rewritable applications enables a 2.9 times faster read-and-write transaction time over EEPROM-based tag ICs. The resulting FeRAM-based tag has a nominally identical communication range for both read and write operations, which is indispensable for data write applications. The evaluated tag communication range with a folded dipole antenna is from 0 m to 4.3 m, at the 953-MHz carrier frequency with 4-W transmitting Effective Isotropic Radiated Power (EIRP) from a reader/writer. The developed tag IC features two circuit blocks to maximize the communication range in 0.35-mum CMOS/FeRAM technology. First is a CMOS-only full-wave rectifier, which can improve the measured efficiency by up to 36.6% by reducing the input parasitic capacitances and optimization of multiplier structure. This efficiency is more than twice that of previously-published results. Second is a low-voltage current-mode ASK demodulator to accommodate a low-breakdown voltage of FeRAM, which converts the ASK power modulation into a linearly modulated current over an incoming power range of 27 dB, corresponding to the entire communication range. The developed demodulator can thus resolve the primary design tradeoff issue between device protection and detection sensitivity in the conventional voltage-mode demodulator

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The use of device simulations to examine substrate-coupling noise induced by the switching of the transistor drain voltages is examined. Methods for reducing such noise are reported. The noise resulting from internal and external parasitics in the path of the substrate current flow is examined for structures with substrate contacts and additional guard rings and for both epitaxial and nonepitaxial substrates. A p/sup +/ guard ring, or substrate contact, between the digital circuits and noise sensitive components is found to be effective for reducing the substrate noise. In heavily doped substrates, a backside contact is an alternative method for noise reduction.<<ETX>>

Technology

A radio frequency identification tag LSI operating with the carrier frequency of 13.56MHz as well as storing nonvolatile information in embedded ferroelectric random access memory (FeRAM) has been developed. A full wave rectifier composed of PMOS transistor diodes and NMOS transistor switches achieves RF-to-DC power conversion efficiency over 54%. The entire 16 kbits write and read transaction time can be reduced to 2.1 sec by the use of FeRAM, which corresponds to 2.2 times speed enhancement over conventional EEPROM based tag LSIs. The communication range of the FeRAM based tag LSI can be effectively improved by storing antitheft information in a ferroelectric nonvolatile flip-flop, which can reduce the power consumption of FeRAM from 27μW to 5μW. The communication range for the antitheft gate system becomes 70 cm.

Simulation of substrate coupling in mixed-signal MOS circuits

This paper presents two circuit implementations for the differential capacitance read scheme (DCRS) in ferroelectric random-access memories (FeRAM). Compared to the conventional read scheme, DCRS achieves a faster read access by activating the sense amplifiers immediately after a wordline is activated. By relying on the capacitance difference instead of the charge difference, DCRS avoids raising the highly capacitive platelines until after the read is complete. We have implemented this scheme in a 0.35-/spl mu/m CMOS+Ferro test chip that includes an array of 256 /spl times/ 32 2T-2C cells. The test chip measures an access time of 45 ns at a power supply of 3 V.

A 13.56 MHz CMOS RF Identification Passive Tag LSI with Ferroelectric Random Access Memory

A differential-capacitance read scheme keeps the plateline voltage constant at ground and begins sensing the stored data immediately after a wordline is raised, hence eliminating the time spent in conventional read schemes in raising the highly capacitive plateline and in charge sharing of the bitlines with the ferroelectric capacitors. The proposed read scheme is used in a 256/spl times/128-bit testchip that features both 2T-2C and 1T-1C cells in 0.35/spl mu/m technology. The read scheme achieves a 40% reduction in access time.

Circuit implementations of the differential capacitance read scheme (DCRS) for ferroelectric random-access memories (FeRAM)

High-speed, area-efficient, and low-power Montgomery modular multipliers for RSA algorithm have been developed for digital signature and user authentication in high-speed network systems and smart card LSIs. The multiplier-accumulators (MAC) in the developed Montgomery modular multipliers have a non-identical multiplicand/multiplier word length organization. This organization can eliminate the bandwidth bottleneck associated with a data memory, and enables to use a single-port memory for area and power reductions. The developed MAC is faster than the conventional identical word length organization due to the shortened critical path. For smart card applications, an area-efficient architecture with 42 kgates can produce 1.2 digital signatures in a second for 2,048-bit key length with the power consumption of 6.8 mW.

A differential-capacitance read scheme for FeRAMs

The buried-oxide (BOX) growth by a high-temperature thermal oxidation of low-dose SIMOX wafers is becoming an indispensable technique for the improvement of material quality, for example, surface roughness and BOX leak path density, as well as the slight decrease in the parasitic capacitance. The physical mechanism of the BOX growth by a thermal oxidation has been investigated for bonded wafers oxidized at 1100/spl deg/C; however, the typical oxidation temperature for low-dose SIMOX wafers is much higher than 1100/spl deg/C. To clarify the oxidation mechanism at higher temperatures and predict the thermally-grown BOX thickness for various conditions, we explore the oxidation process with a simple model based on Deal and Groves analysis.