Daisuke Yamazaki

A Passive UHF RF Identification CMOS Tag IC Using Ferroelectric RAM in 0.35-

A passive UHF RF identification (RFID) tag IC with embedded 2-KB ferroelectric RAM (FeRAM) for rewritable applications enables a 2.9 times faster read-and-write transaction time over EEPROM-based tag ICs. The resulting FeRAM-based tag has a nominally identical communication range for both read and write operations, which is indispensable for data write applications. The evaluated tag communication range with a folded dipole antenna is from 0 m to 4.3 m, at the 953-MHz carrier frequency with 4-W transmitting Effective Isotropic Radiated Power (EIRP) from a reader/writer. The developed tag IC features two circuit blocks to maximize the communication range in 0.35-mum CMOS/FeRAM technology. First is a CMOS-only full-wave rectifier, which can improve the measured efficiency by up to 36.6% by reducing the input parasitic capacitances and optimization of multiplier structure. This efficiency is more than twice that of previously-published results. Second is a low-voltage current-mode ASK demodulator to accommodate a low-breakdown voltage of FeRAM, which converts the ASK power modulation into a linearly modulated current over an incoming power range of 27 dB, corresponding to the entire communication range. The developed demodulator can thus resolve the primary design tradeoff issue between device protection and detection sensitivity in the conventional voltage-mode demodulator

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A passive UHF RFID tag LSI in 0.35mum CMOS with 2kb FeRAM enables the 2.9-times higher 32b read-and-write throughput over an EEPROM-based tag. A CMOS full-wave rectifier improves the power efficiency from 16.6% up to 36.6% by lossless internal Vth cancellation and mirror stack architecture. A current-mode ASK demodulator converts the 15% power modulation into linear current signal over a 27dB dynamic range of the incoming power

Technology

A 1.2V 40Gbit/s 4:1 MUX and 1:4 DEMUX are implemented in a in 90nm digital-compatible standard CMOS technology. The MUX and DEMUX operate from a 1.2V supply and draw 110mA and 52mA, respectively. Experimental results show a clear eye opening of 300mV/sub pp/ for the MUX and that of 540mV/sub pp/ for the DEMUX at 40Gbit/s.

A Passive UHF RFID Tag LSI with 36.6% Efficiency CMOS-Only Rectifier and Current-Mode Demodulator in 0.35/spl mu/m FeRAM Technology

A differential comparator that can sample 40-Gb/s signals and that operates off a single 1.2-V supply was designed and fabricated in 0.11-/spl mu/m standard CMOS technology. It consists of a front-end sampler, a regenerative stage, and a clocked amplifier to provide a small aperture time and a high toggle rate. The clocked amplifier employs a bandwidth modulation technique that switches the feedback gain to reduce the reset time while keeping the effective gain high. We confirmed that the comparator receives a 40-Gb/s data stream at a toggle rate of 10 GHz with bit error rate less than 10/sup -12/ by laboratory measurements.

40Gb/s 4:1 MUX/1:4 DEMUX in 90nm standard CMOS

A differential comparator targeted at receiving 40 Gb/s signals and operating off a single 1.2 V supply was designed and fabricated in 0.11 /spl mu/m CMOS. It comprises a front-end sampler and a regenerative stage with a clocked buffer to achieve a narrow aperture time and a high toggle rate. The regenerative stage output buffer employs an impedance modulation technique based on switching of feedback gain to reduce the reset time while keeping the effective gain high. We confirmed comparator operation with BER less than 10/sup -12/ up to 32 Gb/s at a toggle rate of 8 GHz.

A 40-Gb/s CMOS clocked comparator with bandwidth modulation technique

This paper describes a 25 GHz clock buffer and 50 Gb/s 2-to-1 selector, which are implemented in 90 nm CMOS using 48 nm transistors, and operate off a 1 V supply. An inductor-peaked CMOS inverter is employed for the clock buffer. The selector is equipped with a tail transistor whose gate is switched by the rail-to-rail clock signal produced by the buffer.

A 0.11 /spl mu/m CMOS clocked comparator for high-speed serial communications

The 2:1 selector IC consists of three stages of input buffers, a 2:1 selector stage, and two stages of output buffers. By using multiple inductive peaking and selector architecture to suppress interference, the proposed circuit operates at a data rate of 43Gb/s and it is implemented in 90nm CMOS technology with 48nm transistors.

A 25GHz clock buffer and a 50Gb/s 2:1 selector in 90nm CMOS

The work presented here proposes local I/Q phase correction and carrier leakage suppression techniques for WiMAX transceivers. Local I/Q calibration was able to compensate for process and supply voltage variations, and the measured I/Q phase errors after calibration are within 3 degrees. The measured carrier leakage after calibration substantially meets WiMAX specifications, and the proposed sequence further reduces carrier leakage more than a conventional binary search method. The transceiver with calibration circuits was implemented in a small package, and its performance meets the WiMAX standard.

A 43Gb/s 2:1 selector IC in 90nm CMOS technology

We propose an RF-detector-less carrier leakage suppressor for a WiMAX transmitter. The proposed circuit directly detects the DC offset of a transmitter path and minimizes it, thus reducing carrier leakage. The correct DC-offset feedback to a baseband is achieved by performing an absolute offset comparison after the general binary search technique. The suppressor is integrated in the direct-conversion transceiver of a WiMAX fabricated in 90-nm technology. The measured carrier leakage is better than −32 dBc over the complete transmitter power range.

Local quadrature signal and carrier leakage calibration techniques for a mobile-WiMAX transceiver

We describe the 43-Gb/s and 50-Gb/s operating speed 2-to-1 selector ICs fabricated in 90-nm CMOS technology.