Takamasa Kawanago

Bilayer gate dielectric study by scanning tunneling microscopy

An advanced bilayer gate dielectric stack consisting of Sc2O3∕La2O3∕SiOx annealed in nitrogen at 300°C was studied by scanning tunneling microscopy using bias dependent imaging. By changing the sample bias, electrical properties of different layers of the dielectric stack can be studied. At a sample bias of +3.5V, the conduction band of the La2O3 layer is probed revealing a polycrystalline film with an average grain size of about 27nm, in good agreement with that determined from planar transmission electron microscopy. High conductivity at grain boundaries, due possibly to dangling bonds, can be observed in this layer, as also observed in grain boundary assisted current conduction in metal-oxide-silicon structures. Imaging at a sample bias of −4V probes the interfacial SiOx layer and an amorphouslike image of the interfacial layer is obtained.

Observation of band bending of metal/high-k Si capacitor with high energy x-ray photoemission spectroscopy and its application to interface dipole measurement

Band bendings of Si substrates have been observed using hard x-ray photoemission spectroscopy. With a capability of collecting photoelectrons generated as deep as 40 nm, the binding energy shift in a core level caused by the potential profile at the surface of the substrate results in a spectrum broadening. The broadening is found to be significant when heavily doped substrates are used owing to its steep potential profile. The surface potential of the substrate can be obtained by deconvolution of the spectrum. This method has been applied to observe the band bending profile of metal-oxide-semiconductor capacitors with high-k gate dielectrics. By comparing the band bending profiles of heavily-doped n+- and p+-Si substrates, the interface dipoles presented at interfaces can be estimated. In the case of W gated La2O3/La-silicate capacitor, an interface dipole to shift the potential of −0.45 V has been estimated at La-silicate/Si interface, which effectively reduces the apparent work function of W. On the ot...

EOT of 0.62 nm and High Electron Mobility in La-silicate/Si Structure Based nMOSFETs Achieved by Utilizing Metal-Inserted Poly-Si Stacks and Annealing at High Temperature

This paper reports on the control of the direct-contact La-silicate/Si interface structure with the aim of achieving scaled equivalent oxide thickness (EOT) and small interface state density. The interface state density at the direct-contact La-silicate/Si interface is found to be reduced to 1.6 × 1011 cm-2eV-1 by annealing at 800 °C for 30 min in forming gas ambient, whereas excess silicate reaction concurrently induced a significant increase in EOT. By utilizing metal-inserted poly-Si (MIPS) stacks and their annealing at high temperature, the increase in EOT is drastically suppressed. At the same time, a superior interfacial property is obtained because the Si layer in the MIPS stacks prevents the excess oxygen diffusion from the atmosphere during the annealing process. As a result, the effective electron mobility of 155 cm2/V·s at 1 MV/cm and an EOT of 0.62 nm are successfully achieved by utilizing direct-contact La-silicate/Si structure. This result is comparable with the recorded effective electron mobility achieved by utilizing Hf-based oxides/Si structure. This demonstrates the advantage of our proposed method to realize the scaled EOT with a superior interfacial property for state-of-the-art metal-oxide-semiconductor field-effect transistors.

Interface and electrical properties of Tm2O3 gate dielectrics for gate oxide scaling in MOS devices

The authors analyzed the electrical properties of MOS capacitors with thulium oxide (Tm2O3) gate dielectrics and evaluated the thickness-dependent properties. The authors observed that a thin silicate layer (instead of an SiO2 layer) with a thickness of less than 1 nm had formed between the Tm2O3 and Si substrate after an annealing process at 500 °C. The authors obtained an effective oxide thickness of 0.55 nm with dielectric constants of 18 and 12 for Tm2O3 and its silicate, respectively. The leakage current properties with different thicknesses have revealed sufficient suppression by 2 orders of magnitude from the required levels. However, conduction mechanism analyses and a model to explain the flatband voltage (Vfb) behavior on different thicknesses showed the presence of charged defects in the oxides, which were mostly located at the Tm2O3 and silicate interface. The effective mobility of nFET showed degraded properties by Coulomb scatterings, which were consistent with the Vfb shift. The less reacti...

Electronic trap characterization of the Sc2O3∕La2O3 high-κ gate stack by scanning tunneling microscopy

The tunneling current versus voltage characteristic of the Sc2O3∕La2O3∕SiOx high-κ gate stack is examined using scanning tunneling microscopy in ultrahigh vacuum. Different measurement bias polarities allow information on the location (i.e., in the high-κ or interfacial SiOx layer) of the electronic traps to be extracted. Two types of localized leakage sites may be distinguished. Lowering of the electron barrier height and trap-assisted tunneling are proposed as the two leakage mechanisms.

Utilizing self-assembled-monolayer-based gate dielectrics to fabricate molybdenum disulfide field-effect transistors

In this study, we apply self-assembled-monolayer (SAM)-based gate dielectrics to the fabrication of molybdenum disulfide (MoS2) field-effect transistors. A simple fabrication process involving the selective formation of a SAM on metal oxides in conjunction with the dry transfer of MoS2 flakes was established. A subthreshold slope (SS) of 69 mV/dec and no hysteresis were demonstrated with the ultrathin SAM-based gate dielectrics accompanied by a low gate leakage current. The small SS and no hysteresis indicate the superior interfacial properties of the MoS2/SAM structure. Cross-sectional transmission electron microscopy revealed a sharp and abrupt interface of the MoS2/SAM structure. The SAM-based gate dielectrics are found to be applicable to the fabrication of low-voltage MoS2 field-effect transistors and can also be extended to various layered semiconductor materials. This study opens up intriguing possibilities of SAM-based gate dielectrics in functional electronic devices.

Gate Technology Contributions to Collapse of Drain Current in AlGaN/GaN Schottky HEMT

Contributions of gate metal to electrical characteristics in AlGaN/GaN Schottky HEMT are reported. The focus is on the collapse of drain current associated with Schottky metals. Ni and W gate introduce electrically active defects under the gate metal in AlGaN layer. These electrically active defects induce the current collapse, higher gate leakage current, and frequency dispersion in C-V characteristics. Contrarily, TiN metal seems to mitigate the appearance of such electrically active defects. The observed current collapse is not the permanent but the recoverable degradation by means of light exposure irrespectively of the gate metals, suggesting the involvement of electron trapping on defects, particularly at the gate edge on the drain side where the electric field is the highest. The nitrogen vacancies in the AlGaN layer underneath the Schottky gate are plausible origin that is responsible for the electrically active defects based on the dependence of nitrogen concentration in TiN metal on the current collapse, which can be explained in terms of nitrogen diffusion from the AlGaN layer to the gate metal.

Effect of Postdeposition Annealing Temperatures on Electrical Characteristics of Molecular-Beam-Deposited HfO2 on n-InAs/InGaAs Metal-Oxide-Semiconductor Capacitors

The electrical characteristics of molecular-beam-deposited HfO2/n-InAs/InGaAs metal–oxide–semiconductor capacitors with different postdeposition annealing (PDA) temperatures (400–550 °C) are investigated. Results show that the sample with the PDA temperature of 500 °C exhibits the best capacitance–voltage (C–V) behavior with small frequency dispersion and small hysteresis. The X-ray photoelectron spectroscopy (XPS) spectra show the reduction of the amount of As-related oxides to below the XPS detection level when the PDA temperature is up to 500 °C. As the PDA temperature was increased to above 500 °C, As and In atoms seem to diffuse significantly into HfO2, resulting in the degradation of C–V behavior.

La2O3 gate dielectrics for AlGaN/GaN HEMT

Abstract The annealing temperature dependent electrical characteristics of La2O3 gate dielectrics for W gated AlGaN/GaN high electron mobility transistors (HEMTs) have been characterized. The threshold voltage (Vth) has been found to shift to positive direction with higher temperature annealing, exceeding those of Schottky HEMTs, presumably attributed to the presence of negative fixed charges at the interface between La2O3 and AlGaN layers. At a high temperature annealing over 500 °C, a high dielectric constant (k-value) of 27 has been achieved with poly-crystallization of the La2O3 film, which is useful to limit the reduction in gate capacitance. A high k-value for La2O3 gate dielectrics and the presence of negative charges at the interface are attractive for AlGaN/GaN HEMTs with low gate leakage and normally-off operation.

Polarity dependent breakdown of the high-κ∕SiOx gate stack: A phenomenological explanation by scanning tunneling microscopy

From scanning tunneling microscopy, we present unambiguous evidence of thermally induced localized conduction paths exhibiting an asymmetrical conduction property in the high-κ gate stack. The tunneling current under gate injection biasing is found to be much larger than that under substrate injection biasing after a 700°C postdeposition anneal, i.e., the localized paths exhibit a much lower resistance under gate injection biasing. This finding provides a phenomenological explanation for the polarity dependent breakdown of the high-κ gate stack as observed from electrical stressing of large-area metal-oxide-semiconductor capacitors.