Kenji Yamagata

Control of Grain Boundary Location By Selective Nucleation Over Amorphous Substrates

A selective nucleation based crystal-growth-technique over amorphous substrates is originated. The method manipulates nucleation sites and periods and hence, controls the grain boundary location by modifing the substrate surface. In Si, small Si 3 N 4 nucleation sites are formed, 1–2 pm in diameter, 100 μm in period, over Sio 2 . One Si nucleus is formed exclusively in the small area of Si 3 N 4 by CVD. The highly faceted and periodically located nuclei grow over SiO 2 up to 100 μm in diameter before impingement. A MOS-FET fabricated inside the island operates comparably to the bulk Si control

Epitaxial growth on porous Si for a new bond and etchback silicon-on-insulator

A new bond and etchback silicon-on-insulator (SOI) has been proposed and demonstrated, in which epitaxial layers on porous Si are transferred by bonding and etching back porous Si. The key processes are epitaxial growth on porous Si and selective removal of porous Si. In the epitaxial layers over porous Si, the major defects are stacking faults, which can be reduced to 10 3 to 10 4 /cm 2 by raising the H 2 prebake temperature and lengthening the immersion time in diluted HF prior to the prebake. Bondable smooth surfaces were formed at growth temperatures below 900°C. A highly selective etchant of HF-H 2 O 2 was discovered and enabled us to etch off porous Si with a selectivity of 10 5 , leaving behind epitaxial layers on the oxidized handle wafers. The rough as-etched SOI surface was smooth comparable to that of the commercially available bulk-polished wafer, and boron concentration in the SOI-Si layer was simultaneously decreased to ∼1 x 10 16 /cm 3 , by H 2 annealing. Finally, a uniform SOI layer of 507 nm ±3% across a 5 in. wafer was achieved by this method.

Manipulation of nucleation sites and periods over amorphous substrates

A selective nucleation based crystal growth technique over amorphous substrates is originated. The method manipulates nucleation sites and periods, and hence, controls the grain boundary location by modifying the substrate surface. In Si, Si3 N4 provides artificial nucleation sites, 1–2 μm in diameter, 100 μ m in period, which is surrounded by SiO2 . One Si nucleus is formed exclusively in a small portion of Si3 N4 . The highly faceted and periodically located nuclei grow over SiO2 up to 100 μm in diameter before impingement. A field‐effect transistor fabricated inside the island operates comparably to the bulk Si control.

Selective growth of Si crystals from the agglomerated Si seeds over amorphous substrates

Selective growth of Si crystals over amorphous substrates, seeded by the agglomerated single domained Si crystals is demonstrated. Si crystal seeds are formed from the minutely patterned polycrystalline Si films over amorphous SiO2 by the solid‐state agglomeration phenomenon. Periodically placed seeds are grown selectively up to 100 μm by CVD selective epitaxial growth technique. An n‐channel metal oxide semiconductor (NMOS) transistor is fabricated inside a planarized Si island on a fused quartz substrate and operated with an electron mobility of up to 600 cm2/V s.

Bonding, Splitting and Thinning by Porous Si in ELTRAN®; SOI-Epi Wafer™

ELTRAN is a unique technique to produce the SOI wafers using a porous Si material in semiconductor process. In ELTRAN process, it is required to form the porous Si layer on entire wafer surface uniformly, stably and mass productively without contaminations. In this investigation, we have carried out the simulation of current density distribution to unify the porous layer thickness by finite element method. Canon designed and completed an automatic anodization apparatus. As a result, we could produce the 8 and 6 inches porous Si wafers and ELTRAN SOI wafers stably. And we also developed successfully 300mm ELTRAN SOI wafers with excellent SOI film thickness uniformity.

Fabrication and characterization of CMOSFETs on porous silicon for novel device layer transfer

To develop a new device layer transfer technology with porous layer splitting, CMOS FETs were successfully fabricated on epitaxial layers with different thicknesses over porous silicon for the first time. FETs on more than 300nm thick epitaxial films show satisfactory electrical performance. A fabricated active layer was successfully transferred on a flexible plastic substrate for the first time. Transferred devices also show excellent performance. This technology is applicable to flexible single crystal ICs and to thermal cooling of active layers

Scalability potential in ELTRAN/sup (R)/ SOI-epi wafer

For coming device applications, advanced requirements for silicon-on-insulator (SOI) wafers are increasing. One of the most important items is scalability that includes scaling up of the wafer diameter and scaling down of the SOI layer thickness (t/sub SOI/). 300 mm wafers and ultra thin SOI with t/sub SOI/ less than 100 nm will be required according to the ITRS (SIA, 1999). 300 mm SOI wafers are essential for process cost reduction of the most advanced device applications with shrunken design rules. On the other hand, ultra thin SOI layers are important especially for fully depleted SOI-MOSFETs. In this paper, we applied ELTRAN/sup (R)/ technology (Yonehara et al., 1994) to 300 mm SOI and ultra thin SOI in order to demonstrate the scalability.

High-quality epitaxial layer transfer (ELTRAN) by bond and etch-back of porous Si

The small thickness variation and the high crystalline quality in the SOI films are required for the large scale integration of devices. BESOI is one of the attractive methods due to its layer thickness versatility and productivity particularly in large-scale wafers. Recently, we have reported a novel BESOI method, in which an epitaxial layer on porous Si is transferred onto another handle wafer by bonding and etching back of porous Si (ELTRAN). The structure difference and the abrupt interface between porous and bulk Si gives the very high etching selectivity (10/sup 4/-10/sup 5/), so that it can replace the dopant-sensitive selective etching in the existing BESOI, and allow high-temperature heat treatments (/spl ges/1100/spl deg/C) both to grow the good epitaxial layer and to increase the bonding strength. In this paper, the high etching selectivity and the resultant SOI thickness uniformity are discussed. The crystalline quality of the SOI layer is evaluated by defect delineate etching and p-n junction diodes.