Kensaku Yamamoto

Influence of Threading Dislocations on Lifetime of Gate Thermal Oxide

The reliability of gate oxides is a fundamental issue for realizing SiC MOSFETs. Many reports said that crystal defects shorten the lifetime of the gate oxide. And, epi defects, the basal plane dislocations and threading screw dislocations (TSD) are considered killer defects. However, because of the high TSD density of commercial SiC wafers, the exact relationship between other kinds of dislocations with lifetime has not been revealed. On the other hand, RAF wafers that we developed have low TSD density, so it is easy to evaluate the relationship between other kinds of dislocations and lifetime. By using RAF wafers, in this study, we clarified the relationship between the lifetime of the gate oxide and crystal defects. We fabricated MOS diodes and measured their lifetimes by TDDB (Time Dependent Dielectric Breakdown) measurement. The breakdown points were defined by the photo-emission method. Finally, we classified the defects by TEM (Transmission Electron Microscopy). As the results, it was clarified that threading edge dislocation (TED) decreases the lifetime as does TSD, which earlier reports said. The lifetime of the gate oxide area, in which a TED is included, was shorter by one order of magnitude than a wear-out breakdown. And, the TSD was two orders.

Impact of Al Doping Concentration at Channel Region on Mobility and Threshold Voltage Instability in 4H-SiC Trench N-MOSFETs

The effect of Al doping concentration (NA) at channel regions ranging from 1.0×1017 to 4.0×1017 cm-3 on the effective channel mobility of electron (μeff) and the threshold voltage (Vth) instability under the positive bias-temperature-stress conditions has been investigated througu the use of trench-gate 4H-SiC MOSFETs with m-face (1-100) channel regions. It was found that μeff degraded with an increase in NA. On the other hand, the increase of NA enlarged the Vth instability. These results indicate that NA has a large impact not only on the Vth value but also on the channel resistance and reliability in 4H-SiC trench MOSFETs.

Characteristics of MOS Capacitors with NO and POCl3 Annealed Gate Oxides on (0001), (11-20) and (000-1) 4H-SiC

MOS capacitors have been fabricated on (0001), (11-20) and (000-1) oriented 4H-SiC under different post-oxidation anneal (POA) conditions. 100 MHz conductance measurement shows the generation of very fast donor-type interface traps after NO anneal for both Si-face (0001) and a-face (11-20), but not on C-face (000-1). Fast traps were not observed in POCl3 annealed samples for any orientation. Smallest Dit (at 0.2 eV below conduction band edge) was obtained on Si-face using POCl3 anneal (1.4x1011 cm-2 eV-1), on a-face using NO anneal (2.5x1011 cm-2 eV-1) and on C-face using POCl3 anneal (4.5x1012 cm-2 eV-1).

Effect of N bonding structure in AlON deposited by plasma-assisted atomic layer deposition on electrical properties of 4H-SiC MOS capacitor

We have investigated the effects of the N bonding structure in an AlON layer deposited by plasma-assisted atomic layer deposition (ALD) on the electrical properties of a 4H-SiC MOS structure. The properties of defects in the AlON and SiO2 layers were investigated from the capacitance–voltage and current density–voltage (J–V) characteristics of AlON/SiO2/4H-SiC MOS structures. The density of negatively charged defects in the AlON layer decreases with increasing N content. We found that the leakage current decreases with increasing N content at a low-voltage region from J–V characteristics. The bonding structure in the AlON layer was characterized by X-ray photoelectron spectroscopy. The densities of Al–N and Al–O–N bonds in the AlON layer increase with the N content. In contrast, the density of Al–NO2 bonds decreases with increasing N content. We suggest that the decrease in the defect density in the AlON layer is related to the increasing number of Al–N and Al–O–N bonds. Thus, we concluded that it is important to form Al–N and Al–ON bonds in the AlON layer while suppressing the formation of Al–NO2 bonds.

Effect of Activation Annealing and Reactive Ion Etching on MOS Channel Properties of (11-20) Oriented 4H-SiC

In this paper we have investigated the effect of two key processing steps for the fabrication of 4H-SiC trench gate power MOSFETs, namely activation annealing and reactive ion etching on the MOS interface properties of a-face (11-20) 4H-SiC. By optimizing activation annealing conditions, high channel mobility (µfe) of 111 cm2/V.s, threshold voltage (VT) of 3.5V and subthreshold slope (S) of 194 mV/dec was obtained. However, after reactive ion etching (RIE) of the surface, µfe reduced to 81 cm2/V.s with increase in VT to 5V and S to 331 mV/dec. This is possibly due to increase in interface trap density from 1.8×1012 cm-2 to 3.3×1012 cm-2 after RIE treatment estimated from by MOS gated diode characteristics. Increased trap density contributes to higher coulombic scattering as indicated by the weaker temperature dependence of high field mobility in RIE etched sample.

Effects of nitridation for SiO2/SiC interface on defect properties near the conduction band edge

We have investigated the effects of NO annealing on the electrical properties of a SiO2/4H-SiC interface. The electrical properties of the NO-annealed sample are different from those of the wet-annealed sample. NO or wet annealing generates positive or negative charges, respectively, in the insulator. The interface trap density (D it) near the conduction band edge (E c − 0.1 eV, where E c is the conduction band edge) increases with NO annealing. In contrast, the D it of the NO-annealed sample at around E c − 0.2 eV is lower than that of the wet-annealed sample. The interface state near the conduction band edge in the NO-annealed sample is identified to be of the donor type. Thus, it is considered that the higher D it near the conduction band edge and/or Coulomb scattering due to positive charges causes a decrease in the n-channel mobility in the nitrided SiO2/SiC interface by NO annealing.

Study of Mobility Limiting Mechanisms in (11-20) 4H-SiC NO Annealed MOSFETs

NO annealed Lateral (11-20) MOSFETs were fabricated and mobility limiting mechanisms were investigated by MOS-gated Hall measurements, impedance analysis of MOS capacitor and so on. We have clarified that about 1×1012 cm-2 of inversion electrons are trapped at the interface and mobility is largely limited by Coulombic scattering. We attribute that the Coulombic scattering is caused by electrons trapped at interface states and positive fixed charges, which might be due to donor-like states.

Impact of optical phonon scattering on inversion channel mobility in 4H-SiC trenched MOSFETs

Temperature characteristics of the channel mobility were investigated for 4H-SiC trenched MOSFETs in the range from 30 to 200 °C. The conventional model of channel mobility limited by carrier scattering is based on Si-MOSFETs and shows a greatly different channel mobility from the experimental value, especially at high temperatures. On the other hand, our improved mobility model taking into account optical phonon scattering yielded results in excellent agreement with experimental results. Moreover, the major factors limiting the channel mobility were found to be Coulomb scattering in a low effective field (<0.7 MV/cm) and optical phonon scattering in a high effective field.