Kentaro Matsunaga

Resist edge roughness with reducing pattern size

Recently, resist edge roughness with reducing pattern size has become a serious problem. We investigated the roughness of chemically amplified, positive-tone resists, experimentally. To reduce the roughness, we added a quencher with strong basicity to the resist, and observed sub quarter micron nested lines. As a result, the roughness was improved with increasing the quencher concentration, especially in 0.15 micrometers nested line patterns. Adding quencher was not too much effective for the larger size patterns. The acid concentration in resist was increased by adding quencher, because the nominal dose became large by that. It was also indicated experimentally that generated acid concentration at pattern edge was nearly equal to that of quencher at nominal dose. The nominal dose was determined by quencher concentration. We defined effective acid concentration as remaining acid concentration after quenching. This effective acid concentration increased with increasing quencher concentration too. The roughness seemed to be generated when effective acid concentration profile was lowered. It is indicated that the resist edge roughness with reducing pattern size can be expected from its effective acid concentration profile.

Development of resist material and process for hp-2x-nm devices using EUV lithography

Extreme ultraviolet (EUV) lithography is the leading candidate for the manufacture of semiconductor devices at the hp- 22-nm technology node and beyond. The Selete program covers the evaluation of manufacturability for the EUV lithography process. So, we have begun a yield analysis of hp-2x-nm test chips using the EUV1 full-field exposure tool. However, the resist performance does not yet meet the stringent requirements for resolution limit, sensitivity, and line edge roughness. We reported on Selete standard resist 4 (SSR4) at the EUVL Symposium in 2009. Although it has better lithographic performance than SSR3 does, pattern collapse limits the resolution to hp 28 nm. To improve the resolution, we need to optimize the process so as to prevent pattern collapse. An evaluation of SSR4 for the hp-2x-nm generation revealed that a thinner resist and the use of a TBAH solution for the developer were effective in mitigating this problem. Furthermore, the use of an underlayer and an alternative rinse solution increased the exposure latitude by preventing pattern collapse when the resist is overexposed. These optimizations improved the resolution limit to hp 22 nm.

Development status of EUV resist materials and processing at Selete

The Selete R&D program evaluates the feasibility of the Extreme ultraviolet (EUV) lithography process for manufacturing semiconductor devices. We therefore conducted a yield analysis of hp-2x-nm test chips by using the EUV1 (Nikon) full-field exposure tool. However, the resist performance did not comply with the stringent requirements of ultimate resolution, sensitivity, and line-width roughness. We subsequently reported two new Selete standard resists (SSRs), i.e., SSR6 and SSR7. SSR6 is the polymer resist used in hp-2x-nm test chip evaluation in which an ultimate resolution of 22 nm line-and-space (L/S) pattern was achieved. SSR7 is the first molecular resist that was evaluated for feasibility at Selete. SSR7 is a fullerene based resist with strong etching durability. By using this resist, an ultimate resolution of 24 nm L/S pattern was achieved. We have also evaluated resist processing by using SSRs for hp-2x-nm test chip evaluation. An ultrathin underlayer was evaluated for the improvement of pattern transferability. This optimized ultrathin underlayer was coated on the test chip substrate that was devoid of nano-sized-pinholes, and a fine pattern was observed on this ultrathin underlayer. In the evaluation of the development process, SSRs were evaluated with tetramethylammonium hydroxide (TMAH) and tetrabutylammonium hydroxide (TBAH) developer solutions. In summary, it was clear that the lithographic performance improvement varies depending on the type of polymer resist used with a particular developer solution. Furthermore, a significant improvement in the prevention of pattern collapse was demonstrated using a combination of the TBAH developer solution and alternative rinse solutions.

Applicability of extreme ultraviolet lithography to fabrication of half pitch 35nm interconnects

Extreme ultraviolet lithography (EUVL) is moving into the phase of the evaluation of integration for device fabrication. This paper describes its applicability to the fabrication of back-end-of-line (BEOL) test chips with a feature size of hp 35 nm, which corresponds to the 19-nm logic node. The chips were used to evaluate two-level dual damascene interconnects made with low-k film and Cu. The key factors needed for successful fabrication are a durable multi-stack resist process, accurate critical dimension (CD) control, and usable overlay accuracy for the lithography process. A multi-stack resist process employing 70-nm-thick resist and 25-nm-thick SOG was used on the Metal-1 (M1) and Metal- 2 (M2) layers. The resist thickness for the Via-1 (V1) layer was 80 nm. To obtain an accurate CD, we employed rulebased corrections involving mask CD bias to compensate for flare variation, mask shadowing effects, and optical proximity effects. With these corrections, the CD variation for various 35-nm trench and via patterns was about ± 1 nm. The total overlay accuracy (|mean| ± 3σ) for V1 to M1 and M2 to V1 was below 12 nm. Electrical tests indicate that the uses of Ru barrier metal and scalable porous silica are keys to obtaining operational devices. The evaluation of a BEOL test chip revealed that EUVL is applicable to the fabrication of hp-35-nm interconnects and that device development can be accelerated.

Resolution capability of SFET with slit and dipole illumination

A high-resolution EUV exposure tool is needed to facilitate the development of EUV resists and masks. Since the EUV small-field exposure tool (SFET) has a high numerical aperture (NA = 0.3), low aberration & flare, and excellent stage stability, it should be able to resolve fine L/S patterns for the half-pitch 22-nm & 16-nm nodes. In this study, we evaluated the resolution capability of the SFET and obtained 22-nm L/S patterns with x-slit illumination and clear modulation of 16-nm L/S patterns with x-dipole illumination. The resolution limit of the SFET seems to be about 15 nm. The main cause of pattern degradation in 16-nm L/S is probably resist blur. To obtain good shapes for this pattern size, the resist blur of less than 3.5 nm (σ) is required. The use of y-slit illumination was found to reduce the linewidth roughness (LWR) of resist patterns. Further reduction of the LWR requires a higher image contrast and a smaller flare. Due to the central obscuration, the image contrast of the SFET is sensitive to the change of pupil fill. The degradation in the collector & DMT should be reduced to ensure stable aerial images. This work was supported in part by NEDO.

Performance of EUV molecular resists based on fullerene derivatives

This paper summarizes the development of EUV molecular resists based on fullerene derivatives: the lithographic evaluation results of EUV resists using a small-field exposure tool (SFET). Moreover this is the first report on the application of fullerene-based molecular resists to half-pitch (hp) 3x-nm test device fabrication using a full-field step-and-scan exposure tool (EUV1).

Study on acid diffusion length effect with PAG-blended system and anion-bounded polymer system

Fundamental studies on polymer bounded PAG and polymer - PAG blend type were carried out with the viewpoint of dissolution property, lithographic performance, and blur. These materials were prepared to be able to directly compare and to discuss the difference between blend and bounded PAG, with different PAG loading amount. Dissolution property revealed the clear difference of these materials tendency to the PAG loading amount variation. Lithographic performance difference corresponds to the dissolution property difference, and there found the strategy to improve lithographic performance with polymer bounded PAG type resist. Blur study suggests the advantage in polymer bounded PAG in resolution.

Alternative resist processes for LWR reduction in EUVL

The main development issue for EUV resists is how to concurrently achieve high sensitivity, resolution below 22-nm half-pitch (hp), and low line width roughness (LWR) in the required fine patterns. Sensitivity and resolution continue to be improved through advances in EUV resist material research. However, through the material-approach, LWR remains a difficult issue. Thus, LWR-reduction from the point of view of alternative resist processes was investigated. As a result, LWR improvement was obtained utilizing alternative developer and rinse solutions. However, a difference in the LWR-reduction effect of these processes depending on the type of resist material used was observed.

LWR reduction in low-k1 ArF-immersion lithography

Line width roughness (LWR) reduction is a critical issue for low k1 ArF immersion lithography. Various approaches such as materials, exposure technology and the track process have been performed for LWR reduction during lithography process. It was reported that the post-development bake process had good performance for LWR reduction (1). However, the post-development bake process induced large CD change owing to the degradation of large isolated resist pattern. Therefore post-development process with small iso-dense bias is required in low k1 ArF immersion lithography. The resist smoothing process is one of the candidates for LWR reduction with small iso-dense bias. This method whereby the resist pattern surface is partially melted in organic-solvent atmosphere was shown to have a significant LWR reduction effect on resist patterns. This paper reports on the application of the resist smoothing process to the ArF immersion resist pattern after development. It was found that the resist smoothing process was effective to reduce LWR for ArF immersion resist. As a result of LWR trace from after development to after the hard mask etching process, the effect of LWR reduction with the resist smoothing process continued after the hard mask etching process. Furthermore CD change of large isolated patterns with the smoothing process was smaller than in the case of post-development bake process. We confirmed that the resist smoothing process is an effective method for decreasing LWR in ArF immersion lithography.

Process liability evaluation for beyond 22nm node using EUVL

Extreme ultraviolet lithography (EUVL) is the most promising candidate for the manufacture of devices with a half pitch of 32 nm and beyond. We are now evaluating the process liability of EUVL in view of the current status of lithography technology development. In a previous study, we demonstrated the feasibility of manufacturing 32-nm-node devices by means of a wafer process that employed the EUV1, a full-field step-and-scan exposure tool. To evaluate yield, a test pattern was drawn on a multilayer resist and exposed. After development, the pattern was replicated in SiO2 film by etching, and metal wires were formed by a damascene process. Resolution enhancement is needed to advance to the 22- nm node and beyond, and a practical solution is off-axis illumination (OAI). This paper presents the results of a study on yield improvement that used a 32-nm-node test chip, and also clarifies a critical issue in the use of EUVL in a wafer process for device manufacture at the 22-nm node and beyond.