Kento Kimura

A 60-GHz sub-sampling frequency synthesizer using sub-harmonic injection-locked quadrature oscillators

This paper presents a 60-GHz sub-harmonic injection-locked quadrature frequency synthesizer with subsampling operation. This allows the proposed synthesizer to achieve relatively lower in-band phase noise through the use of sub-sampling operation, as well as good out-of-band phase noise through the use of sub-harmonic injection. The proposed synthesizer has been implemented in a standard 65-nm CMOS technology. It can support all 60-GHz channels and achieves a phase noise of -115dBc/Hz at 10MHz offset. The sub-sampling operation helps reducing an integrated jitter from 12ps to 2.1ps. It consumes 20.2mW and 14mW from a 20GHz sub-sampling phase-locked loop (SS-PLL) and a quadrature injection-locked oscillator (QILO), respectively.

25.2 A 2.2GHz −242dB-FOM 4.2mW ADC-PLL using digital sub-sampling architecture

This paper presents an all-digital phase-locked loop (PLL) using a voltage-domain digitization realized by an analog-to-digital converter (ADC). It consists of an 18b Class-C digitally-controlled oscillator (DCO), 4b comparator, digital loop filter (DLF), and frequency-locked loop (FLL). Implemented in 65nm CMOS technology, the proposed PLL reaches an in-band phase noise of -112dBc/Hz and an RMS jitter of 380fs at 2.2GHz oscillation frequency. An FOM of -242dB has been achieved with a power consumption of only 4.2 mW.

A Fractional- N Sub-Sampling PLL using a Pipelined Phase-Interpolator With an FoM of -250 dB

A fractional-N sub-sampling PLL architecture based on pipelined phase-interpolator and Digital-to-Time-Converter (DTC) is presented in this paper. The combination of pipelined phase-interpolator and DTC enables efficient design of the multi-phase generation mechanism required for the fractional operation. This technique can be used for designing a fractional-N PLL with low in-band phase noise and low spurious tones with low power consumption. The short-current-free pipelined phase-interpolator used in this work is capable of achieving high-linearity with low-power while minimizing the intrinsic jitter. A number of other circuit techniques and layout techniques are also employed in this design for ensuring high-performance operation with minimal chip area and power consumption. The proposed fractional-N PLL is implemented in standard 65 nm CMOS technology. The PLL has an operating range of 600 MHz from 4.34 GHz to 4.94 GHz. In fractional-N mode, the proposed PLL achieves -249.5 dB FoM and less than -59 dBc fractional spurs.

A Low-Power Low-Noise mm-Wave Subsampling PLL Using Dual-Step-Mixing ILFD and Tail-Coupling Quadrature Injection-Locked Oscillator for IEEE 802.11ad

This paper presents a low-power low-noise 60 GHz frequency synthesizer using a 20 GHz subsampling phase-locked loop (SS-PLL) and a 60 GHz tail-coupling quadrature injection-locked oscillator (QILO) which results in a lower in-band phase noise and out-of-band phase noise, respectively. To save battery life, dual-step-mixing injection-locked frequency divider (ILFD) enhances locking range for high division ratio. Moreover, tail cross-coupling technique in a QILO helps boost negative transconductance (-gm) of the 60 GHz QILO which allows the use of larger inductance for power reduction. Implemented in 65 nm CMOS, it can cover required channels from 58.32 to 64.80 GHz with quadrature outputs. It consumes 24.2 and 7.8 mW from 20 GHz SS-PLL and QILO, respectively. The proposed synthesizer achieves -78.5; dBc/Hz at 100 kHz offset, -122 dBc/Hz at 10 MHz offset, and a figure-of-merit (FoM) of -236 dB.

13.6 A 42Gb/s 60GHz CMOS transceiver for IEEE 802.11ay

It is predicted that the required wireless communication capacity will become 1000 times higher every 10 years. Many wireless standards are under discussion to satisfy the unprecedented capacity requirement. For example, the IEEE802.11ay standard is targeting over 100Gb/s data-rate by using the 60GHz band. Unfortunately, the channel bandwidth of 2.16GHz for the 60GHz band is not wide enough to realize such a high data-rate, so a channel-bonding capability is strongly demanded to extend the data-rate as well as 64-QAM support, achieving 42.24Gb/s. To realize 4-channel bonding operation with 64QAM, fine and wideband I/Q mismatch calibration is one of the remaining issues. In addition, an 8b 14.08GS/s ADC is required to support 42.24Gb/s, which is usually realized by a massive time-interleaved ADC, and needs unreasonably large power consumption. In this work, a frequency-interleaved (FI) architecture is employed for the 60GHz transceiver-side to mitigate the wideband I/Q mismatch issue and the ADC requirement. In addition, an asymmetric quadrature injection-locked oscillator (QILO) is proposed to widen the locking range.

19.5 An HCI-healing 60GHz CMOS transceiver

The research of 60GHz CMOS transceivers has bloomed due to their capability of achieving low-cost multi-Gb/s short-range wireless communications [1]. Considering practical use of the 60GHz CMOS transceivers, longer operation lifetime with high output power is preferred to provide reliable products. Unfortunately, as indicated in [2], the output power capability of the transmitter will gradually degrade due to the hot-carrier-injection (HCI) effects in the standard CMOS transistors at large-signal operation (e.g. power amplifiers). It is because the inherently large voltage swing at the output of the power amplifiers (PAs) is the main source of the HCI damage. Unfortunately, a thick-oxide transistor, a common solution for reliability issues at lower frequencies, cannot be utilized for 60GHz CMOS PA design due to its limited maximum oscillation frequency (fmax).

A pulse-driven LC-VCO with a figure-of-merit of −192dBc/Hz

This paper proposes a LC-VCO with a pulse-driven cross-coupled pair. The proposed pulse driving technique has the ability to achieve class-C like current waveform while reducing the Amplitude-Modulation to Phase-Modulation (A-PM) conversion by parasitic capacitance of the active devices. A VCO is implemented using the proposed technique in a standard 0.18um CMOS technology. It oscillates at a carrier frequency of 3.6GHz with a 0.65-V supply. The measured phase noise is -124 dBc/Hz @ 1MHz-offset with a power consumption of 2.05mW. The figure-of-merit (FoM) is -192 dBc/Hz.

An LO-buffer-less 60-GHz CMOS transmitter with oscillator pulling mitigation

A low-power and small-area 60-GHz CMOS transmitter with oscillator pulling mitigation is presented. The subharmonic injection locking technique for the suppression of pulling effects is analyzed and demonstrated. The transmitter fabricated in a 65nm CMOS process achieves 7.04-Gb/s data rate with an EVM performance of −25 dB in 16QAM. The whole transmitter consumes 210 mW from a 1.2-V supply and occupies a core area of 0.82 mm2 including a PLL.

A fractional-N sub-sampling PLL using a pipelined phase-interpolator with a FoM of −246dB

This paper presents a fractional-N PLL working in sub-sampling mode using a pipelined phase-interpolator. The proposed pipelined phase-interpolator can achieve high phase linearity with very low power consumption. The fractional-N sub-sampling PLL is implemented in a standard 65nm CMOS technology. The PLL works at a frequency ranging from 4.3GHz to 4.9GHz while consuming 3.3mW. The measured in-band phase noise in fractional-N mode is -114dBc/Hz at 400kHz offset from the carrier, while working with a bandwidth of approximately 2MHz. The combination of high-precision low-power phase-interpolation technique and the sub-sampling technique realizes a high-performance fractional-N frequency synthesizer with the highest reported FoM.

24.9 A 128-QAM 60GHz CMOS transceiver for IEEE802.11ay with calibration of LO feedthrough and I/Q imbalance

The 60GHz carrier with 9GHz bandwidth enables ultra-high-speed wireless communication in recent years [1–4]. To meet the demand from rapidly-increasing data traffic, the IEEE802.11ay standard is one of the most promising candidates aiming for 100Gb/s data-rate. Both higher-order digital modulation such as 128QAM and channel bonding at 60GHz are considered to be used in the IEEE802.11ay standard. However, the more severe requirements of LO feedthrough (LOFT) and image-rejection ratio (IMRR) have to be satisfied, so much higher accuracy in built-in calibration circuitry is required across the entire 9GHz spectrum for LOFT and I/Q imbalance calibration to achieve the required EVM.