Teerachot Siriburanon

A Compact, Low-Power and Low-Jitter Dual-Loop Injection Locked PLL Using All-Digital PVT Calibration

This paper presents a low-jitter, low-power and a small-area injection-locked all-digital PLL (IL-ADPLL). It consists of a dual-loop and a dual-VCO architecture in which one VCO (Replica) is placed in a TDC-less synthesizable ADFLL to provide continuous tracking of voltage and temperature variations. The other VCO (main) shares the control voltage with the replica VCO but is placed outside the loop and is injection-locked to lower its jitter and accurately set its frequency to the desired one. This approach avoids timing problems in the conventional ILPLL since the injection-locked VCO is placed outside the feedback loop. It also achieves a low power and a small area, due to the absence of a power hungry TDC and an area-consuming loop filter, while tracking any PVT variations. The IL-ADPLL is implemented in a 65 nm CMOS process and measurement results show that it achieves a 0.7ps RMS jitter at 1.2 GHz while having 1.6 mW and 0.97 mW power consumption with and without intermittent operation resulting in an FOM of -243 dB. It also consumes an area of only 0.022 mm2 resulting in the best performance-area trade-off system presented up-to-date.

A Fully Synthesizable All-Digital PLL With Interpolative Phase Coupled Oscillator, Current-Output DAC, and Fine-Resolution Digital Varactor Using Gated Edge Injection Technique

This paper presents a fully synthesizable phase-locked loop (PLL) based on injection locking, with an interpolative phase-coupled oscillator, a current output digital-to-analog converter (DAC), and a fine resolution digital varactor. All circuits that make up the PLL are designed and implemented using digital standard cells without any modification, and automatically Place-and-routed (P&R) by a digital design flow without any manual placement. Implemented in a 65 nm digital CMOS process, this work occupies only 110 μm × 60 μm layout area, which is the smallest PLL reported so far to the best knowledge of the authors. The measurement results show that this work achieves a 1.7 ps RMS jitter at 900 MHz output frequency while consuming 780 μW DC power.

A 0.022mm 2 970µW dual-loop injection-locked PLL with −243dB FOM using synthesizable all-digital PVT calibration circuits

For modern SoC systems, stringent requirements on on-chip clock generators include low area, low power consumption, environmental insensitivity, and the lowest possible jitter performance. Multiplying Delay-Locked Loop (MDLL) [1-2], subharmonically injection-locked techniques [3], and sub-sampling techniques [4-5] can significantly improve the random jitter characteristics of a clock generator. However, in order to guarantee their correct operation and optimal performance over process-voltage-temperature (PVT) variations, each method requires additional calibration circuits, which impose difficult-to-meet timing constraints. In the case of an injection-locked PLL (IL-PLL), a free-running frequency calibration is required. However, the output of an injection-locked oscillator is always fixed at the desired frequency, so a shift in the free-running frequency (e.g. caused by temperature and voltage variations) cannot be simply compensated for by using a frequency-locked loop (FLL). Therefore, we propose the use of a dual-loop topology with one free-running voltage-controlled oscillator (VCO) as a replica VCO placed inside a FLL for tracking temperature and voltage drift. The other VCO (the main VCO) is injection locked for producing a low-jitter clock, while the free-running frequency shift can be compensated for by the replica loop. The method provides robust output over temperature and voltage variations.

A Sub-Harmonic Injection-Locked Quadrature Frequency Synthesizer With Frequency Calibration Scheme for Millimeter-Wave TDD Transceivers

This paper proposes a sub-harmonic injection-locked frequency synthesizer with frequency calibration scheme for millimeter-wave Time-division Duplexing (TDD) transceivers. The proposed synthesizer is capable of supporting all 60 GHz channels (58.1-65 GHz) including channel-bonding defined by 60 GHz wireless standards for short-range high-speed wireless communications. In order to guarantee a robust performance over process-voltage-temperature (PVT) variations of the conventional frequency synthesizer, a frequency calibration scheme is proposed to automatically correct a frequency drift of quadrature injection locked oscillators. Implemented by a 65 nm CMOS process, the frequency synthesizer achieves a typical phase noise of -117 dBc/Hz @ 10 MHz offset from a carrier frequency of 61.56 GHz while consuming 72 mW from a 1.2 V supply. The calibration system consumes 65 mW additionally.

A 60-GHz sub-sampling frequency synthesizer using sub-harmonic injection-locked quadrature oscillators

This paper presents a 60-GHz sub-harmonic injection-locked quadrature frequency synthesizer with subsampling operation. This allows the proposed synthesizer to achieve relatively lower in-band phase noise through the use of sub-sampling operation, as well as good out-of-band phase noise through the use of sub-harmonic injection. The proposed synthesizer has been implemented in a standard 65-nm CMOS technology. It can support all 60-GHz channels and achieves a phase noise of -115dBc/Hz at 10MHz offset. The sub-sampling operation helps reducing an integrated jitter from 12ps to 2.1ps. It consumes 20.2mW and 14mW from a 20GHz sub-sampling phase-locked loop (SS-PLL) and a quadrature injection-locked oscillator (QILO), respectively.

A 13.2% locking-range divide-by-6, 3.1mW, ILFD using even-harmonic-enhanced direct injection technique for millimeter-wave PLLs

This paper presents a wide-locking-range, low-power, Injection-Locked Frequency Divider (ILFD) using even-harmonic-enhanced direct injection technique which can operate with a high division ratio of 4 and 6. The proposed ILFD has been fabricated in a 65nm CMOS process with a core area of 0.002mm2. The proposed ILFD achieves the widest measured locking range reported of 4.3 GHz (13.2%) for a divide-by-6 operation with a power consumption of only 3.1mW without any tuning mechanism. Moreover, it also achieves 5.7GHz (28.5%) for divide-by-4 operation while consuming only 3.1mW. Combining its multi-division and tuning capability, the dividing capability ranges from 14.0-38.0GHz while consuming 2.8 to 5.4mW.

25.2 A 2.2GHz −242dB-FOM 4.2mW ADC-PLL using digital sub-sampling architecture

This paper presents an all-digital phase-locked loop (PLL) using a voltage-domain digitization realized by an analog-to-digital converter (ADC). It consists of an 18b Class-C digitally-controlled oscillator (DCO), 4b comparator, digital loop filter (DLF), and frequency-locked loop (FLL). Implemented in 65nm CMOS technology, the proposed PLL reaches an in-band phase noise of -112dBc/Hz and an RMS jitter of 380fs at 2.2GHz oscillation frequency. An FOM of -242dB has been achieved with a power consumption of only 4.2 mW.

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Inductors on Locally Semi-Insulated Si Substrate by Helium-3 Bombardment for RF CMOS Integrated Circuits

inductors by creating locally semi-insulating substrate areas. A dose of