Tomohiro Ueno

A Fully Synthesizable All-Digital PLL With Interpolative Phase Coupled Oscillator, Current-Output DAC, and Fine-Resolution Digital Varactor Using Gated Edge Injection Technique

This paper presents a fully synthesizable phase-locked loop (PLL) based on injection locking, with an interpolative phase-coupled oscillator, a current output digital-to-analog converter (DAC), and a fine resolution digital varactor. All circuits that make up the PLL are designed and implemented using digital standard cells without any modification, and automatically Place-and-routed (P&R) by a digital design flow without any manual placement. Implemented in a 65 nm digital CMOS process, this work occupies only 110 μm × 60 μm layout area, which is the smallest PLL reported so far to the best knowledge of the authors. The measurement results show that this work achieves a 1.7 ps RMS jitter at 900 MHz output frequency while consuming 780 μW DC power.

20.3 A 64-QAM 60GHz CMOS transceiver with 4-channel bonding

This paper presents a 64-QAM 60GHz CMOS transceiver, which achieves a TX-to-RX EVM of -26.3dB and can transmit 10.56Gb/s in all four channels defined in IEEE802.11ad/WiGig. By using a 4-bonded channel, 28.16Gb/s can be transmitted in 16QAM. The front-end consumes 251mW and 220mW from a 1.2-V supply in transmitting and receiving mode, respectively. Figure 20.3.1 shows the 60GHz direct-conversion front-end design. The transmitter consists of a 6-stage PA, differential preamplifiers, I/Q passive mixers and a quadrature injection-locked oscillator (QILO). The receiver consists of a 4-stage LNA, differential amplifiers, I/Q double-balanced mixers, a QILO, and baseband amplifiers. A direct-conversion architecture is employed for both TX and RX because of wide-bandwidth capability [1]. The LO consists of the 60GHz QILO and a 20GHz PLL. The 60GHz QILO works as a frequency tripler with the integrated 20GHz PLL. It can generate 7 carrier frequencies with a 36/40MHz reference, 58.32GHz(ch.1), 60.48GHz(ch.2), 62.64GHz(ch.3), and 64.80GHz(ch.4) defined in IEEE802.11ad/WiGig, 59.40GHz(ch.1-2), 61.56GHz(ch.2-3), and 63.72GHz(ch.3-4) for the channel bonding.

A 60-GHz sub-sampling frequency synthesizer using sub-harmonic injection-locked quadrature oscillators

This paper presents a 60-GHz sub-harmonic injection-locked quadrature frequency synthesizer with subsampling operation. This allows the proposed synthesizer to achieve relatively lower in-band phase noise through the use of sub-sampling operation, as well as good out-of-band phase noise through the use of sub-harmonic injection. The proposed synthesizer has been implemented in a standard 65-nm CMOS technology. It can support all 60-GHz channels and achieves a phase noise of -115dBc/Hz at 10MHz offset. The sub-sampling operation helps reducing an integrated jitter from 12ps to 2.1ps. It consumes 20.2mW and 14mW from a 20GHz sub-sampling phase-locked loop (SS-PLL) and a quadrature injection-locked oscillator (QILO), respectively.

25.2 A 2.2GHz −242dB-FOM 4.2mW ADC-PLL using digital sub-sampling architecture

This paper presents an all-digital phase-locked loop (PLL) using a voltage-domain digitization realized by an analog-to-digital converter (ADC). It consists of an 18b Class-C digitally-controlled oscillator (DCO), 4b comparator, digital loop filter (DLF), and frequency-locked loop (FLL). Implemented in 65nm CMOS technology, the proposed PLL reaches an in-band phase noise of -112dBc/Hz and an RMS jitter of 380fs at 2.2GHz oscillation frequency. An FOM of -242dB has been achieved with a power consumption of only 4.2 mW.

13.6 A 42Gb/s 60GHz CMOS transceiver for IEEE 802.11ay

It is predicted that the required wireless communication capacity will become 1000 times higher every 10 years. Many wireless standards are under discussion to satisfy the unprecedented capacity requirement. For example, the IEEE802.11ay standard is targeting over 100Gb/s data-rate by using the 60GHz band. Unfortunately, the channel bandwidth of 2.16GHz for the 60GHz band is not wide enough to realize such a high data-rate, so a channel-bonding capability is strongly demanded to extend the data-rate as well as 64-QAM support, achieving 42.24Gb/s. To realize 4-channel bonding operation with 64QAM, fine and wideband I/Q mismatch calibration is one of the remaining issues. In addition, an 8b 14.08GS/s ADC is required to support 42.24Gb/s, which is usually realized by a massive time-interleaved ADC, and needs unreasonably large power consumption. In this work, a frequency-interleaved (FI) architecture is employed for the 60GHz transceiver-side to mitigate the wideband I/Q mismatch issue and the ADC requirement. In addition, an asymmetric quadrature injection-locked oscillator (QILO) is proposed to widen the locking range.

A 2.2 GHz

This paper presents an all-digital phase-locked loop (AD-PLL) using a voltage-domain digitization realized by an analog-to-digital converter (ADC) instead of adopting a traditional time-to-digital converter (TDC) which usually suffers from a tradeoff in resolution and power consumption. It consists of an 18 bit class-C digitally controlled oscillator (DCO), a 4 bit comparator, a digital loop filter (DLF), and a frequency-locked loop (FLL). Implemented in 65 nm CMOS technology, the proposed PLL reaches an in-band phase noise of -112 dBc/Hz and an RMS jitter of 380 fs at a carrier frequency of 2.2 GHz. A figure of merit (FoM) of -242 dB was achieved with a power consumption of only 4.2 mW.

-242\;\text{dB}

The research of 60GHz CMOS transceivers has bloomed due to their capability of achieving low-cost multi-Gb/s short-range wireless communications [1]. Considering practical use of the 60GHz CMOS transceivers, longer operation lifetime with high output power is preferred to provide reliable products. Unfortunately, as indicated in [2], the output power capability of the transmitter will gradually degrade due to the hot-carrier-injection (HCI) effects in the standard CMOS transistors at large-signal operation (e.g. power amplifiers). It is because the inherently large voltage swing at the output of the power amplifiers (PAs) is the main source of the HCI damage. Unfortunately, a thick-oxide transistor, a common solution for reliability issues at lower frequencies, cannot be utilized for 60GHz CMOS PA design due to its limited maximum oscillation frequency (fmax).

-FOM 4.2 mW ADC-PLL Using Digital Sub-Sampling Architecture

A low-power and small-area 60-GHz CMOS transmitter with oscillator pulling mitigation is presented. The subharmonic injection locking technique for the suppression of pulling effects is analyzed and demonstrated. The transmitter fabricated in a 65nm CMOS process achieves 7.04-Gb/s data rate with an EVM performance of −25 dB in 16QAM. The whole transmitter consumes 210 mW from a 1.2-V supply and occupies a core area of 0.82 mm2 including a PLL.

19.5 An HCI-healing 60GHz CMOS transceiver

This paper presents a small area, low power, fully synthesizable PLL with a current output DAC and an interpolative-phase coupled oscillator using edge injection technique for on-chip clock generation. A prototype PLL is fabricated in a 65nm digital CMOS process, achieves a 1.7-ps integrated jitter at 0.9 GHz and consumes 0.78 mW leading to an FOM of -236.5 dB while only occupying an area of 0.0066 mm2. It achieves the best performance-area trade-off.

An LO-buffer-less 60-GHz CMOS transmitter with oscillator pulling mitigation

This paper presents a low power and low noise sub-harmonically injection-locked PLL using a 20GHz sub-sampling PLL (SS-PLL) and a quadrature injection locked oscillator (QILO). Lower in-band phase noise and out-of-band phase noise have been achieved through the sub-sampling phase detection and sub-harmonic injection techniques, respectively. Implemented in a 65nm CMOS, this work can support all 60GHz channels and achieves a phase noise of -115dBc/Hz at 10MHz offset while consuming 20.2mW and 14mW from the 20GHz SS-PLL and the QILO, respectively.