Mitsuasa Takahashi

A 5 to 130 V level shifter composed of thin gate oxide dual terminal drain PMOSFETS

The market demand for high performance and cost effective flat panel display (FPD: e.g. plasma display, electroluminescent display) system has mandated that FPD driver designs need to be more cost effective. The driver plays a vital role in determining the FPD (system) performance and manufacturing cost as well as the panel itself. The driver is basically a device which can translate digital data signals (typically 5 V-logic) to the series of high voltage outputs (60 to 300 V) for the panel electrode load array. To reduce the manufacturing cost, this paper describes a study of the novel 5 to 130 V level shifter with Dual Terminal Drain PMOSFETs (DTDPMOS) for the first time. To adopt this level shifter, although the driver IC consists of both high and low voltage CMOS, the high voltage CMOS can be realized with the same thin gate oxide as the low voltage CMOS.

An intelligent power device using poly-Si sandwiched wafer bonding technique

A new simple isolation structure has been realized by using poly-Si sandwiched wafer bonding technique. We confirmed that the poly-Si layer enabled the bonded interface to be void-free and electrically perfect, and had the effect that it enabled the reverse recovery time of the parasitic diode of Vertical DMOSFET (VDMOS) to be short. In the new structure, the isolation capabilities were adequate to integrate 60 V VDMOS and control circuits on the same chip. Especially, the parasitic bipolar action has been suppressed. We evaluated an intelligent power device which uses this technique and have confirmed the availability of the new isolation structure.

Application of partially bonded SOI structure to an intelligent power device having vertical DMOSFET

In recent years, many types of Intelligent Power Devices (IPDs) have been developed. A key technology of developing the IPDs is the isolation between power device and control circuit. The isolation structures and its manufacturing methods are required to be more efficient and cost effective. We had been developed a low side switch IPD having Vertical DMOSFET (VDMOS) output by using poly-crystalline silicon sandwiched wafer bonding (PSB) technique. In this PSB structure, it is easy to achieve void-free bonding because the extremely flat poly-crystalline silicon (poly-Si) layer surface and the single-crystalline silicon (Si) substrate surface are bonded together. However, the PSB structure is still expensive. To reduce the fabrication cost, we have made a study of the direct bonding without poly-Si and proposed a new SOI structure named partially bonded (PB) structure. This paper reports the evaluation results that we applied the PB structure to a low side switch IPD for the first time.

Void-Free Bonded SOI Substrates for High-Voltage, High-Current Vertical DMOS-Type Power ICs

New isolated structures for intelligent power ICs were developed using a wafer bonding technique. These structures have partial buried oxide films for dielectric isolation and buried poly-Si layers for wafer bonding. In this bonding technique, bonding surfaces are a poly-Si layer and a crystalline silicon surface; this combination of bonding surfaces leads to void-free bonding. The electrical perfection of the vertical output device in the new structure was obtained by diffusing antimony into the poly-Si layer. These results indicate that intelligent power ICs can be manufactured by using the new structure.

Extraction of off-set region length for off-set gate MOSFETs

Abstract The off-set region length of off-set gate MOSFETs is extracted from the linear relations between the total channel resistance and the design off-set region length. This extraction method uses the values obtained by the conventional two-step regression line method. The influence of MOSFET channel resistance in the total channel resistance measurements is removed by extrapolating the gate bias of the MOSFET to infinity. Both experimental data and two-dimensional device simulation confirm that this extraction can accurately determine the off-set region length.